Zero wait state

Zero wait state is a feature of a processor or computer architecture in which the processor does not have to wait to perform memory access. Non-zero… (More)
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Topic mentions per year

Topic mentions per year

1988-2013
012319882013

Papers overview

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2013
2013
  • Vincent T. Poole
  • 2013
In early 1991, Honeywell delivered three RH-1 7 SOA based flight computers to complete the AST III program in support of a… (More)
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2001
2001
A flash memory with flexible multi-partition architecture allows programming or erasing in one partition while reading from… (More)
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2001
2001
* This work was supported by the U.S. DOE Contract No. DE-AC05-84-ER40150 Abstract A Dual Digital Signal Processing VME Board was… (More)
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2001
2001
* This work was supported by the U.S. DOE Contract No. DE-AC05-84-ER40150 Abstract A Dual Digital Signal Processing VME Board was… (More)
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Review
1999
Review
1999
This paper will give an overview of the digital control laboratory developed at the University of Illinois Urbana/Champaign… (More)
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1997
1997
A 3.3V 16Mb nonvolatile memory has read and write operations fully DRAM-compatible except a longer RAS precharge time after write… (More)
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1996
1996
A 32 kB, semi-associative bit dimension, L1 cache test site uses 0.5 /spl mu/m 2.5 V CMOS. The technology features an Leff of 0… (More)
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1988
1988
The authors examine the cache architecture of the Apollo DN4000 workstation, which utilizes a virtual cache to provide a cost… (More)
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