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X86-64
Known as:
IA-64t
, Intel EM64T
, PML4
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x86-64 (also known as x64, x86_64 and AMD64) is the 64-bit version of the x86 instruction set. It supports vastly larger amounts (theoretically, 264…
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Related topics
Related topics
50 relations
(formerly Pro/ENGINEER)
32-bit
AROS Research Operating System
Advanced Synchronization Facility
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2020
2020
2.1 Zen 2: The AMD 7nm Energy-Efficient High-Performance x86-64 Microprocessor Core
T. Singh
,
S. Rangarajan
,
+4 authors
Alex Schaefer
IEEE International Solid-State Circuits…
2020
Corpus ID: 215799538
Codenamed “Zen 2”, the AMD next-generation, high-efficiency core is an x86-64 design, fabricated in an energy-efficient TSMC 7nm…
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2018
2018
Research of cross-platform stream symmetric ciphers implementation
A. Kuznetsov
,
V. Frolenko
,
E. Eremin
,
O. Zavgorodnia
International Conference on Dependable Systems…
2018
Corpus ID: 49730421
In this paper, the modern symmetric stream ciphers Enocoro, Decim, Grain, HC, MUGI, Mickey, Rabbit, RC-4, Salsa20, SNOW2.0…
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Highly Cited
2014
Highly Cited
2014
Supporting x86-64 address translation for 100s of GPU lanes
Jason Power
,
M. Hill
,
D. Wood
International Symposium on High-Performance…
2014
Corpus ID: 10756551
Efficient memory sharing between CPU and GPU threads can greatly expand the effective set of GPGPU workloads. For increased…
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Highly Cited
2010
Highly Cited
2010
Characterizing the energy consumption of data transfers and arithmetic operations on x86−64 processors
Daniel Molka
,
D. Hackenberg
,
R. Schöne
,
Matthias S. Müller
International Conference on Green Computing
2010
Corpus ID: 7383683
The energy efficiency of computer systems is influenced by many interdependent aspects. To asses the efficiency, typical…
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Highly Cited
2010
Highly Cited
2010
An x86-64 core implemented in 32nm SOI CMOS
Ravi Jotwani
,
Sriram Sundaram
,
+5 authors
S. Naffziger
IEEE International Solid-State Circuits…
2010
Corpus ID: 1031646
The 32nm implementation of an AMD x86-64 core [1,2,5], occupies 9.69mm2, contains more than 35 million transistors (excluding L2…
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Highly Cited
2010
Highly Cited
2010
New Software Speed Records for Cryptographic Pairings
M. Naehrig
,
R. Niederhagen
,
P. Schwabe
International Conference on Cryptology and…
2010
Corpus ID: 3155033
This paper presents new software speed records for the computation of cryptographic pairings. More specifically, we present…
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Highly Cited
2009
Highly Cited
2009
Relaxed memory models: an operational approach
G. Boudol
,
G. Petri
ACM-SIGACT Symposium on Principles of Programming…
2009
Corpus ID: 2034487
Memory models define an interface between programs written in some language and their implementation, determining which behaviour…
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Highly Cited
2007
Highly Cited
2007
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
Matt T. Yourst
IEEE International Symposium on Performance…
2007
Corpus ID: 444710
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim…
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Highly Cited
2006
Highly Cited
2006
Utilizing IOMMUs for Virtualization in Linux and Xen Muli
Muli Ben-Yehuda
,
Jon Mason
,
Orran Krieger
2006
Corpus ID: 368435
IOMMUs are hardware devices that translate device DMA addresses to proper machine physical addresses. IOMMUs have long been used…
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Highly Cited
2006
Highly Cited
2006
How Far Can We Go on the x64 Processors?
M. Matsui
Fast Software Encryption Workshop
2006
Corpus ID: 15764730
This paper studies the state-of-the-art software optimization methodology for symmetric cryptographic primitives on the new 64…
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