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Verilog-A

Known as: VerilogA 
Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS.
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Papers overview

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2015
2015
The run-time for circuit-level CDM ESD simulation can be prohibitively long. By leveraging the specific properties of the problem… 
2015
2015
The main challenge in ternary content addressable memory (TCAM) design is to reduce the power consumption associated with… 
2013
2013
In this paper, a behavioral current-voltage model with intermediate states is proposed for analog applications of unipolar… 
2013
2013
In this work we will show for the first time the case of an IC robust to on-chip IEC 61000-4-2 ESD level events and, yet… 
2009
2009
The collector current Ic of a bipolar transistor does not instantaneously respond to changes in applied base-emitter voltage Vbe… 
2009
2009
In this paper, we present a FinFET compact model and its associated parameter extraction methodology. This explicit model… 
2008
2008
El gran avance tecnologico producido en los ultimos anos en el ambito de las comunicaciones, ha incrementado la complejidad de… 
2008
2008
A fully-customized phase change memory (PCM) model for circuit simulation has been developed and implemented in Verilog-A… 
2007
2007
In this paper we discuss an approach for the implementation of non-linear electromechanical and RF models of complete RF-MEMS… 
2002
2002
This paper discusses aBlox - a specification notation for high-level synthesis of mixed-signal systems. aBlox addresses three…