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Verilog-A
Known as:
VerilogA
Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS.
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Electronic circuit simulation
Ken Kundert
Programming language reference
SystemVerilog
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
A Data-Driven Verilog-A ReRAM Model
I. Messaris
,
Alexander Serb
,
S. Stathopoulos
,
A. Khiat
,
S. Nikolaidis
,
T. Prodromakis
IEEE Transactions on Computer-Aided Design of…
2018
Corpus ID: 53772850
The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical…
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2016
2016
Large-Signal Model of Graphene Field- Effect Transistors—Part II: Circuit Performance Benchmarking
F. Pasadas
,
D. Jiménez
IEEE Transactions on Electron Devices
2016
Corpus ID: 26145301
This paper presents a circuit performance benchmarking using the large-signal model of graphene FET reported in Part I of this…
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Highly Cited
2016
Highly Cited
2016
Compact Model of Dielectric Breakdown in Spin-Transfer Torque Magnetic Tunnel Junction
You Wang
,
H. Cai
,
+5 authors
Weisheng Zhao
IEEE Transactions on Electron Devices
2016
Corpus ID: 30524836
Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed…
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Highly Cited
2015
Highly Cited
2015
VTEAM: A General Model for Voltage-Controlled Memristors
S. Kvatinsky
,
Misbah Ramadan
,
E. Friedman
,
A. Kolodny
IEEE Transactions on Circuits and Systems II…
2015
Corpus ID: 206655679
Memristors are novel electrical devices used for a variety of applications, including memory, logic circuits, and neuromorphic…
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Highly Cited
2015
Highly Cited
2015
A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements
C.S. Lee
,
E. Pop
,
A. Franklin
,
W. Haensch
,
H. Wong
IEEE Transactions on Electron Devices
2015
Corpus ID: 23320107
We present a data-calibrated compact model of carbon nanotube (CNT) FETs (CNTFETs) based on the virtual-source (VS) approach…
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Review
2014
Review
2014
Tunnel FET technology: A reliability perspective
S. Datta
,
Huichu Liu
,
N. Vijaykrishnan
Microelectron. Reliab.
2014
Corpus ID: 8425226
2014
2014
MIT virtual source GaNFET‐high voltage (MVSG‐HV) model: A physics based compact model for HV‐GaN HEMTs
U. Radhakrishna
,
T. Imada
,
T. Palacios
,
D. Antoniadis
2014
Corpus ID: 122791211
A new physics based transport and charge model for long channel GaN HEMTs is proposed. The model is based on the concept of…
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Highly Cited
2013
Highly Cited
2013
Magnetic Adder Based on Racetrack Memory
Hong-Phuc Trinh
,
Weisheng Zhao
,
Jacques-Olivier Klein
,
Yue Zhang
,
D. Ravelosona
,
C. Chappert
IEEE Transactions on Circuits and Systems I…
2013
Corpus ID: 5536057
The miniaturization of integrated circuits based on complementary metal oxide semiconductor (CMOS) technology meets a significant…
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Highly Cited
2009
Highly Cited
2009
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage
S. Chong
,
K. Akarvardar
,
+4 authors
H. Wong
IEEE/ACM International Conference on Computer…
2009
Corpus ID: 13163870
We present a hybrid nanoelectromechanical (NEM)/CMOS static random access memory (SRAM) cell, in which the two pull-down…
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2007
2007
PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs
Weimin Wu
,
Xin Li
,
+8 authors
J. Watts
IEEE Custom Integrated Circuits Conference
2007
Corpus ID: 2328072
This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new…
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