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Verification and validation
Known as:
Verfiable
, VV
, Operational qualification
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Verification and validation are independent procedures that are used together for checking that a product, service, or system meets requirements and…
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Related topics
Related topics
50 relations
Acceptance testing
Agent-based model
Authentication
BIOS
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Broader (1)
Systems engineering
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2009
Highly Cited
2009
Adaptive Management of Virtualized Resources in Cloud Computing Using Feedback Control
Qiang Li
,
Qinfen Hao
,
Limin Xiao
,
Zhoujun Li
First International Conference on Information…
2009
Corpus ID: 18383564
Cloud computing as newly emergent computing environment offers dynamic flexible infrastructures and QoS guaranteed services in…
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Highly Cited
2006
Highly Cited
2006
Model Checking Russian Cards
Hans van Ditmarsch
,
W. Hoek
,
R. V. D. Meyden
,
J. Ruan
MoChArt@CONCUR/SPIN
2006
Corpus ID: 16219004
Highly Cited
2005
Highly Cited
2005
Hierarchical interface-based supervisory control-part II: parallel case
R. Leduc
,
M. Lawford
,
W. Wonham
IEEE Transactions on Automatic Control
2005
Corpus ID: 9129007
In this paper, we present a hierarchical method that decomposes a discrete-event system (DES) into a high-level subsystem which…
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Highly Cited
2000
Highly Cited
2000
iCAR: an integrated cellular and ad-hoc relay system
C. Qiao
,
Hongyi Wu
Proceedings Ninth International Conference on…
2000
Corpus ID: 8099002
Ever increasing data traffic and limited capacity are major causes for congestion in current cellular systems. This paper…
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Highly Cited
1996
Highly Cited
1996
Modeling and control of a multi-phase induction machine with structural unbalance part II. Field-oriented control and experimental verification
Y. Zhao
,
T. Lipo
1996
Corpus ID: 114454183
Field-oriented control techniques for a multi-phase induction machine with an unbalanced stator winding structure is presented in…
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Highly Cited
1995
Highly Cited
1995
Advanced Verification Techniques Based on Learning
J. Jain
,
R. Mukherjee
,
M. Fujita
Design Automation Conference
1995
Corpus ID: 11612769
Design verification poses a very practical problem during circuit synthesis. Learning based verification techniques prove to be…
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Highly Cited
1994
Highly Cited
1994
A new statistical model for traffic generated by VBR coders for television on the broadband ISDN
M. Frater
,
J. Arnold
,
P. Tan
IEEE Trans. Circuits Syst. Video Technol.
1994
Corpus ID: 42528567
Many techniques have been proposed for modeling source rates generated by variable bit rate video coders. However, little work…
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Highly Cited
1983
Highly Cited
1983
Testing by Verifying Walsh Coefficients
A. K. Susskind
IEEE transactions on computers
1983
Corpus ID: 1732147
Testing of logic networks by verifying the Walsh coefricients of the outputs is explored. Measurement of one of these can detect…
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Highly Cited
1972
Highly Cited
1972
A Note on Three-Valued Logic Simulation
M. Breuer
IEEE transactions on computers
1972
Corpus ID: 43629740
In this note we discuss a few attributes and pitfalls of three-valued (0, 1, u) digital logic simulation. The areas covered…
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Highly Cited
1965
Highly Cited
1965
Effect of a finite-word-length computer in a sampled-data feedback system
J. Knowles
,
R. Edwards
1965
Corpus ID: 60469473
When a digital computer acts as the compensating element of a sampled-data feedback system, the system performance is degenerated…
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