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Transistor model

Known as: Transistor Models, Transistor parameters 
The modern transistor has an internal structure that exploits complex physical mechanisms. Device design requires a detailed understanding of how… 
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Related topics

Related topics

22 relations
BIBO stabilityBandwidth (signal processing)Curve fittingElectronic circuit simulation

Broader (1)

Electronic engineering

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Drain E-Field Manipulation in AlGaN/GaN HEMTs by Schottky Extension Technology
The proposed hybrid Schottky-ohmic drain structure is analyzed in detail for AlGaN/GaN power high-electron mobility transistors… 
Highly Cited
2012
Highly Cited
2012
Broad-Bandwidth, Electrically Small Antenna Augmented With an Internal Non-Foster Element
A broad-bandwidth, electrically small, near-field resonant parasitic (NFRP) dipole antenna has been designed, analyzed, and… 
2012
2012
Study of Injection Locking With Amplitude Perturbation and Its Effect on Pulling of Oscillator
Injection locking characteristics of oscillators are studied both qualitatively and analytically and the closed-form expressions… 
Highly Cited
2011
Highly Cited
2011
Complementary Ring Oscillator Exclusively Prepared by Means of Gravure and Flexographic Printing
A complementary ring oscillator has been prepared using exclusively fast and continuous rotary printing methods, namely, gravure… 
Highly Cited
2006
Highly Cited
2006
Analysis of emitter (source)-coupled multivibrators
The popular emitter-coupled multivibrator and its MOS variant are analyzed using the classical discontinuity theory. Accurate… 
Highly Cited
2004
Highly Cited
2004
Monolithic Integration of Carbon Nanotube Devices with Silicon MOS Technology
An integrated circuit combining single-walled carbon nanotube (SWNT) devices with n-channel metal oxide semiconductor (NMOS… 
1999
1999
Analyzing the switching behavior of ESD-protection transistors by very fast transmission line pulsing
1997
1997
Interconnect Scaling Scenario Using A Chip Level Interconnect Model
This paper describes an interconnect scaling scenario, which considers the impact of metal aspect ratio, pitch at each layer and… 
1986
1986
The Static Noise Margin of SRAM cells
A simulation method is presented which makes it possible to analyze the stability of SRAM cells in terms of Static Noise Margin… 
1975
1975
Substrate fed logic
A novel form of integrated injection logic (I/SUP 2/L) is described, in which the device structure has been designed specifically… 
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