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Transistor model
Known as:
Transistor Models
, Transistor parameters
The modern transistor has an internal structure that exploits complex physical mechanisms. Device design requires a detailed understanding of how…
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Related topics
Related topics
22 relations
BIBO stability
Bandwidth (signal processing)
Curve fitting
Electronic circuit simulation
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Broader (1)
Electronic engineering
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Impact of Process Variations on Reliability and Performance of 32-nm 6T SRAM at Near Threshold Voltage
L. Kou
,
W. H. Robinson
IEEE Computer Society Annual Symposium on VLSI
2014
Corpus ID: 13882958
Power consumption has become a major concern of integrated circuit (IC) design, especially for SRAM design. Reducing the supply…
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2008
2008
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects
Vinita V. Deodhar
,
Jeffrey A. Davis
IEEE Transactions on Circuits and Systems Part 1…
2008
Corpus ID: 4598521
The simultaneous application of voltage scaling, repeater insertion, and wire sizing is proposed in this paper to achieve high…
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2005
2005
Electrical stresses on ultra-thin gate oxide SOI MOSFETs after irradiation
A. Cester
,
S. Gerardin
,
A. Paccagnella
,
E. Simoen
,
C. Claeys
IEEE Transactions on Nuclear Science
2005
Corpus ID: 45502854
We present the first experimental data about the wear-out of a 0.1 /spl mu/m partially depleted SOI CMOS technology after heavy…
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Highly Cited
2004
Highly Cited
2004
Monolithic Integration of Carbon Nanotube Devices with Silicon MOS Technology
Yu-Chih Tseng
,
Peiqi Xuan
,
+4 authors
H. Dai
2004
Corpus ID: 1560670
An integrated circuit combining single-walled carbon nanotube (SWNT) devices with n-channel metal oxide semiconductor (NMOS…
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2002
2002
Integrated PIN photodiodes in high-performance BiCMOS technology
M. Fortsch
,
H. Zimmermann
,
W. Einbrodt
,
K. Bach
,
H. Pless
Digest. International Electron Devices Meeting,
2002
Corpus ID: 34472958
We attain a PIN photodiode combining high responsivity, fast response and low capacitance in BiCMOS technology. Only a slight…
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1987
1987
Delay Optimization of Combinational Static CMOS Logic
M. Hofmann
,
J. K. Kim
24th ACM/IEEE Design Automation Conference
1987
Corpus ID: 14782511
Several methods for increasing the speed of combinational static CMOS circuits, including techniques for partitioning gates on…
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1987
1987
A Subthreshold Conduction Model for Circuit Simulation of Submicron MOSFET
P. Chan
,
R. Liu
,
S. K. Lau
,
Mario Pinto-Guedes
IEEE Transactions on Computer-Aided Design of…
1987
Corpus ID: 9267747
A circuit simulation model for subthreshold conduction of MOSFET is developed. This model employs a novel interpolation scheme to…
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1987
1987
Optimum crystallographic orientation of submicrometer CMOS devices operated at low temperatures
M. Aoki
,
K. Yano
,
T. Masuhara
,
S. Ikeda
,
S. Meguro
IEEE Transactions on Electron Devices
1987
Corpus ID: 22324436
The dependence of submicrometer-channel CMOS performance on surface orientation is measured for LDD devices at both 300 and 77 K…
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1986
1986
The Static Noise Margin of SRAM cells
F. List
European Solid-State Circuits Conference
1986
Corpus ID: 21431668
A simulation method is presented which makes it possible to analyze the stability of SRAM cells in terms of Static Noise Margin…
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1975
1975
Substrate fed logic
V. Blatt
,
P. Walsh
,
L. W. Kennedy
1975
Corpus ID: 61488407
A novel form of integrated injection logic (I/SUP 2/L) is described, in which the device structure has been designed specifically…
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