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Transistor model

Known as: Transistor Models, Transistor parameters 
The modern transistor has an internal structure that exploits complex physical mechanisms. Device design requires a detailed understanding of how… 
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Related topics

Related topics

22 relations
BIBO stabilityBandwidth (signal processing)Curve fittingElectronic circuit simulation

Broader (1)

Electronic engineering

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Impact of Process Variations on Reliability and Performance of 32-nm 6T SRAM at Near Threshold Voltage
Power consumption has become a major concern of integrated circuit (IC) design, especially for SRAM design. Reducing the supply… 
2008
2008
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects
The simultaneous application of voltage scaling, repeater insertion, and wire sizing is proposed in this paper to achieve high… 
2005
2005
Electrical stresses on ultra-thin gate oxide SOI MOSFETs after irradiation
We present the first experimental data about the wear-out of a 0.1 /spl mu/m partially depleted SOI CMOS technology after heavy… 
Highly Cited
2004
Highly Cited
2004
Monolithic Integration of Carbon Nanotube Devices with Silicon MOS Technology
An integrated circuit combining single-walled carbon nanotube (SWNT) devices with n-channel metal oxide semiconductor (NMOS… 
2002
2002
Integrated PIN photodiodes in high-performance BiCMOS technology
We attain a PIN photodiode combining high responsivity, fast response and low capacitance in BiCMOS technology. Only a slight… 
1987
1987
Delay Optimization of Combinational Static CMOS Logic
Several methods for increasing the speed of combinational static CMOS circuits, including techniques for partitioning gates on… 
1987
1987
A Subthreshold Conduction Model for Circuit Simulation of Submicron MOSFET
A circuit simulation model for subthreshold conduction of MOSFET is developed. This model employs a novel interpolation scheme to… 
1987
1987
Optimum crystallographic orientation of submicrometer CMOS devices operated at low temperatures
The dependence of submicrometer-channel CMOS performance on surface orientation is measured for LDD devices at both 300 and 77 K… 
1986
1986
The Static Noise Margin of SRAM cells
A simulation method is presented which makes it possible to analyze the stability of SRAM cells in terms of Static Noise Margin… 
1975
1975
Substrate fed logic
A novel form of integrated injection logic (I/SUP 2/L) is described, in which the device structure has been designed specifically… 
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