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Transactional Synchronization Extensions
Known as:
RTM
, Intel TSX
, Restricted Transactional Memory
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Transactional Synchronization Extensions (TSX) is an extension to the x86 instruction set architecture (ISA) that adds hardware transactional memory…
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Related topics
Related topics
23 relations
Advanced Synchronization Facility
Broadwell (microarchitecture)
CPUID
Cache coherence
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Broader (3)
Parallel computing
Transaction processing
Transactional memory
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2019
Review
2019
Reinforcing Meltdown Attack by Using a Return Stack Buffer
Taehyun Kim
,
Young-joo Shin
IEEE Access
2019
Corpus ID: 209853260
Meltdown is a microarchitectural side-channel attack that extracts sensitive data in the kernel space of operating systems (OSs…
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2016
2016
Support of research vessels in the Antarctic with NRT radar information: an innovative service at DLR's Antarctic station GARS O’Higgins
Kathrin Höppner
,
B. Schättler
,
+5 authors
Christine Wesche
2016
Corpus ID: 132190971
On their journeys through areas with large layers of sea ice even vessels of high ice class or icebreakers could get into trouble…
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2015
2015
Amalgamated Lock-Elision
Y. Afek
,
A. Matveev
,
Oscar Moll
,
N. Shavit
International Symposium on Distributed Computing
2015
Corpus ID: 9069718
Hardware lock-elision HLE introduces concurrency into legacy lock-based code by optimistically executing critical sections in a…
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2014
2014
Early Experience on Transactional Execution of Java TM Programs Using Intel R © Transactional Synchronization Extensions
Richard M. Yoo
,
S. Viswanathan
,
Vivek Deshpande
,
C. Hughes
,
Shirish Aundhe
2014
Corpus ID: 16390672
This paper applies Intel R © Transactional Synchronization Extensions (Intel R © TSX) to elide Java monitor locks. By utilizing…
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2014
2014
A Study of the Potential of Intel's Transactional Synchronization Extensions for Hybrid Transactional Memory
Mike Dai Wang
2014
Corpus ID: 61806159
A Study of the Potential of Intel’s Transactional Synchronization Extensions for Hybrid Transactional Memory Mike Dai Wang Master…
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2013
2013
Opportunities and pitfalls of multi-core scaling using hardware transaction memory
Zhaoguo Wang
,
Hao Qian
,
Haibo Chen
,
Jinyang Li
Asia Pacific Workshop on Systems
2013
Corpus ID: 18075819
Hardware transactional memory, which holds the promise to simplify and scale up multicore synchronization, has recently become…
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2013
2013
379 Performance Optimizations for TTI RTM on GPU based Hybrid Architectures
A. Narang
,
Suraj Kumar
,
+4 authors
T. Rabben
2013
Corpus ID: 3541907
There has been an ever increasing gap between energy demand and supply of oil and gas worldwide due to multiple challenges…
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2013
2013
Ownership Structure and CEO Compensation in North America: A Combined Study Ap-proach of NYSE and TSX/S&P Index compa-nies
Y. Mohammed
2013
Corpus ID: 15934731
This research had investigated ownership structure and its impact on CEO compensation system in TSX/S&P and NYSE indexes…
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2008
2008
A TOPSAR Processing Algorithm Based on Extended Chirp Scaling: Evaluation with TerraSAR-X Data
P. Prats
,
A. Meta
,
R. Scheiber
,
J. Mittermayer
,
A. Moreira
,
J. Sanz-Marcos
2008
Corpus ID: 55066114
This paper presents an efficient phase preserving processor for the TOPS (Terrain Observation by Progressive Scans) imaging mode…
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2004
2004
Modelling Stock Returns in the G-7 and in Selected CEE Economies: A Non-Linear GARCH Approach
Balázs Égert
,
Yosra Koubaa
2004
Corpus ID: 54986628
This paper investigates conditional variance patterns in daily return series of stock market indices in the G-7 and 6 selected…
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