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Transactional Synchronization Extensions
Known as:
RTM
, Intel TSX
, Restricted Transactional Memory
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Transactional Synchronization Extensions (TSX) is an extension to the x86 instruction set architecture (ISA) that adds hardware transactional memory…
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Related topics
Related topics
23 relations
Advanced Synchronization Facility
Broadwell (microarchitecture)
CPUID
Cache coherence
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Broader (3)
Parallel computing
Transaction processing
Transactional memory
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
New possibilities using TSX and TDX in support of sea ice use
D. Dammann
,
H. Eicken
,
+5 authors
Joshua Jones
2018
Corpus ID: 135056273
Sea ice travel and on-ice operations are important for Arctic coastal communities and industrial operations. Recent rapid changes…
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2017
2017
POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support
Arnamoy Bhattacharyya
,
Mike Dai Wang
,
+5 authors
C. Amza
ACM SIGPLAN Symposium on Principles & Practice of…
2017
Corpus ID: 11004854
In this work, we introduce and experimentally evaluate a new hybrid software-hardware Transactional Memory prototype based on…
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2017
2017
FGSCM: A Fine-Grained Approach to Transactional Lock Elision
Gustavo José de Sousa
,
Alexandro Baldassin
Symposium on Computer Architecture and High…
2017
Corpus ID: 5639288
Speculative Lock Elision (SLE) is a technique that allows critical sections to be executed optimistically by eliding the lock…
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2014
2014
A Study of the Potential of Intel's Transactional Synchronization Extensions for Hybrid Transactional Memory
Mike Dai Wang
2014
Corpus ID: 61806159
A Study of the Potential of Intel’s Transactional Synchronization Extensions for Hybrid Transactional Memory Mike Dai Wang Master…
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2014
2014
Early Experience on Transactional Execution of Java TM Programs Using Intel R © Transactional Synchronization Extensions
R. Yoo
,
S. Viswanathan
,
Vivek Deshpande
,
C. Hughes
,
Shirish Aundhe
2014
Corpus ID: 16390672
This paper applies Intel R © Transactional Synchronization Extensions (Intel R © TSX) to elide Java monitor locks. By utilizing…
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2014
2014
Reduced Hardware Lock Elision
Y. Afek
2014
Corpus ID: 17219224
Hardware lock elision (HLE) concurrently executes lock critical sections as hardware transactions, but fallbacks to the original…
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2013
2013
379 Performance Optimizations for TTI RTM on GPU based Hybrid Architectures
A. Narang
,
Suraj Kumar
,
+4 authors
T. Rabben
2013
Corpus ID: 3541907
There has been an ever increasing gap between energy demand and supply of oil and gas worldwide due to multiple challenges…
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2012
2012
Supporting Intel Transactional Synchronization Extensions in QEMU
S. Dabdoub
,
Stephen Tu
2012
Corpus ID: 29836986
Concurrent programming in shared memory multiprocessor (SMP) systems is challenging. One of the difficulties is that programmers…
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2009
2009
Global ENVISAT ASAR and coastal TerraSAR X Measurements of Sea State for validation of Ocean Wave Models
S. Lehner
,
Xiao-Ming Li
,
S. Brusch
,
T. Bruns
,
W. Rosenthal
2009
Corpus ID: 132581273
Satellite Synthetic Aperture Radar (SAR) images are acquired independent of light and weather conditions on a global scale…
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2006
2006
Diebold TSx Evaluation SECURITY ALERT: May 11, 2006 Critical Security Issues with Diebold TSx
Harri Hursti
2006
Corpus ID: 267837780
vulnerabilities are