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Transactional Synchronization Extensions
Known as:
RTM
, Intel TSX
, Restricted Transactional Memory
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Transactional Synchronization Extensions (TSX) is an extension to the x86 instruction set architecture (ISA) that adds hardware transactional memory…
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Related topics
Related topics
23 relations
Advanced Synchronization Facility
Broadwell (microarchitecture)
CPUID
Cache coherence
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Broader (3)
Parallel computing
Transaction processing
Transactional memory
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2015
Highly Cited
2015
Protecting Private Keys against Memory Disclosure Attacks Using Hardware Transactional Memory
Le Guan
,
Jingqiang Lin
,
Bo Luo
,
Jiwu Jing
,
Jing Wang
IEEE Symposium on Security and Privacy
2015
Corpus ID: 14757390
Cryptography plays an important role in computer and communication security. In practical implementations of cryptosystems, the…
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Highly Cited
2014
Highly Cited
2014
Self-Tuning Intel Transactional Synchronization Extensions
Nuno Diegues
,
P. Romano
International Conference on Automation and…
2014
Corpus ID: 13584122
Transactional Memory was recently integrated in Intel processors under the name TSX. We show that its performance can be…
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2014
2014
Software-improved hardware lock elision
Y. Afek
,
A. Levy
,
Adam Morrison
ACM SIGACT-SIGOPS Symposium on Principles of…
2014
Corpus ID: 16645370
With hardware transactional memory (HTM) becoming available in mainstream processors, lock-based critical sections may now…
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Highly Cited
2014
Highly Cited
2014
Improving in-memory database index performance with Intel® Transactional Synchronization Extensions
Tomas Karnagel
,
R. Dementiev
,
+4 authors
Wolfgang Lehner
International Symposium on High-Performance…
2014
Corpus ID: 206710977
The increasing number of cores every generation poses challenges for high-performance in-memory database systems. While these…
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Highly Cited
2014
Highly Cited
2014
Using restricted transactional memory to build a scalable in-memory database
Zhaoguo Wang
,
Hao Qian
,
Jinyang Li
,
Haibo Chen
European Conference on Computer Systems
2014
Corpus ID: 3484052
The recent availability of Intel Haswell processors marks the transition of hardware transactional memory from research toys to…
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Highly Cited
2014
Highly Cited
2014
Invyswell: A hybrid transactional memory for Haswell's restricted transactional memory
I. Calciu
,
Justin Emile Gottschlich
,
T. Shpeisman
,
Gilles A. Pokam
,
Maurice Herlihy
International Conference on Parallel…
2014
Corpus ID: 2767319
The Intel Haswell processor includes restricted transactional memory (RTM), which is the first commodity-based hardware…
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2014
2014
Concurrent and consistent virtual machine introspection with hardware transactional memory
Yutao Liu
,
Yubin Xia
,
Haibing Guan
,
B. Zang
,
Haibo Chen
International Symposium on High-Performance…
2014
Corpus ID: 1312505
Virtual machine introspection, which provides tamperresistant, high-fidelity “out of the box” monitoring of virtual machines, has…
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2013
2013
Opportunities and pitfalls of multi-core scaling using hardware transaction memory
Zhaoguo Wang
,
Hao Qian
,
Haibo Chen
,
Jinyang Li
Asia Pacific Workshop on Systems
2013
Corpus ID: 18075819
Hardware transactional memory, which holds the promise to simplify and scale up multicore synchronization, has recently become…
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2012
2012
Flight Dynamics Operations of the TanDEM-X Formation
R. Kahle
,
B. Schlepp
,
Saika Aida
,
M. Kirschner
,
M. Wermuth
2012
Corpus ID: 128979969
Since end of 2010 the German TerraSAR-X and TanDEM-X satellites are routinely operated as the first configurable single-pass…
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2011
2011
Interferometric coherence analysis with high resolution space-borne synthetic aperture radar
Sang‐Hoon Hong
,
S. Wdowinski
IEEE Asia-Pacific Conference on Synthetic…
2011
Corpus ID: 23460919
Recently high spatial resolution space-borne synthetic aperture radar (SAR) systems with various polarizations have launched and…
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