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Tile processor
Tile processors are multicore or manycore chips that contain one-dimensional, or more commonly, two-dimensional arrays of identical tiles. Each tile…
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3 relations
Broader (1)
Central processing unit
Multi-core processor
TILEPro64
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Real-time video denoising on multicores and GPUs with Kalman-based and Bilateral filters fusion
S. G. Pfleger
,
P. Plentz
,
Rodrigo C. O. Rocha
,
Alyson D. Pereira
,
M. Castro
Journal of Real-Time Image Processing
2017
Corpus ID: 5324115
In the context of video processing, image noise caused by acquisition, transfer and image compression can be attenuated by video…
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2016
2016
Barrel time-of-flight detector for the PANDA experiment at FAIR
L. Gruber
,
S. Brunner
,
J. Marton
,
H. Orth
,
K. Suzuki
2016
Corpus ID: 119301810
Highly Cited
2014
Highly Cited
2014
Fort-NoCs: Mitigating the threat of a compromised NoC
D. Ancajas
,
Koushik Chakraborty
,
Sanghamitra Roy
51st ACM/EDAC/IEEE Design Automation Conference…
2014
Corpus ID: 207212303
In this paper, we uncover a novel and imminent threat to an emerging computing paradigm: MPSoCs built with 3rd party IP NoCs. We…
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2011
2011
Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor
I. Choi
,
Minshu Zhao
,
Xu Yang
,
D. Yeung
IEEE Computer Architecture Letters
2011
Corpus ID: 2988075
This paper describes our experience with profiling and optimizing physical locality for the distributed shared cache (DSC) in…
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2009
2009
Cognitive Radio baseband processing on a reconfigurable platform
Qiwei Zhang
,
A. Kokkeler
,
G. Smit
,
Karel H. G. Walters
Phys. Commun.
2009
Corpus ID: 42782258
Highly Cited
2007
Highly Cited
2007
On-Chip Interconnection Architecture of the Tile Processor
D. Wentzlaff
,
Patrick Griffin
,
+7 authors
A. Agarwal
IEEE Micro
2007
Corpus ID: 871932
IMesh, the tile processor architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D…
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2007
2007
On-Chip Interconnection Architecture of the Tile Processor
WentzlaffDavid
,
GriffinPatrick
,
+7 authors
AgarwalAnant
2007
Corpus ID: 215883163
iMesh, the Tile Processor Architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D…
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1996
1996
Morphological Analyzer as Syntactic Parser
Gábor Prószéky
COLING
1996
Corpus ID: 16981400
We describe how a simple parser can be built on the basis of morphology and a morphological analyzer. Our initial conditions have…
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1986
1986
Multi‐TeV muon colliders
D. Neuffer
1986
Corpus ID: 14992377
The possibility that muons may be used in a future generation of high‐energy high‐luminosity μ+ μ− and μ‐p colliders is presented…
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1978
1978
Travel of microorganisms from a septic tile
T. Viraraghavan
Water, Air, and Soil Pollution
1978
Corpus ID: 127209579
An investigation was carried out to monitor the horizontal travel of indicator microorganism from the end of a septic tile in the…
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