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Silicon on insulator
Known as:
Semiconductor on Insulator
, SOI device
, Buried Oxide
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Silicon on insulator (SOI) technology refers to the use of a layered silicon–insulator–silicon substrate in place of conventional silicon substrates…
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Related topics
Related topics
50 relations
A-RAM
AMD 10h
Broadway (microprocessor)
Bulldozer (microarchitecture)
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2013
Highly Cited
2013
Understanding the effect of PCB layout on circuit performance in a high frequency gallium nitride based point of load converter
D. Reusch
,
J. Strydom
Applied Power Electronics Conference
2013
Corpus ID: 47558221
The introduction of enhancement mode gallium nitride based power devices such as the eGaN®FET offers the potential to achieve…
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Highly Cited
2013
Highly Cited
2013
UTBB FD-SOI: A process/design symbiosis for breakthrough energy-efficiency
P. Magarshack
,
P. Flatresse
,
G. Cesana
Design, Automation and Test in Europe
2013
Corpus ID: 15887065
UTBB FD-SOI technology has become mainstream within STMicroelectronics, with the objective to serve a wide spectrum of mobile…
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Highly Cited
2006
Highly Cited
2006
A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor
Hwa-Joon Oh
,
S. M. Müller
,
+9 authors
S. Dhong
IEEE Journal of Solid-State Circuits
2006
Corpus ID: 10427825
The floating-point unit (FPU) in the synergistic processor element (SPE) of a CELL processor is a fully pipelined 4-way single…
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Highly Cited
2004
Highly Cited
2004
Ultrahigh-density silicon nanobridges formed between two vertical silicon surfaces
M. Islam
,
S. Sharma
,
T. Kamins
,
R. S. Williams
2004
Corpus ID: 16116336
We report simultaneous lateral growth of a high density of highly oriented, metal-catalyzed silicon nanowires on a patterned…
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Highly Cited
2004
Highly Cited
2004
High inversion current in silicon nanowire field effect transistors
S. Koo
,
A. Fujiwara
,
Jinhua Han
,
E. Vogel
,
C. Richter
,
J. Bonevich
2004
Corpus ID: 55263936
Silicon nanowire (SiNW) field effect transistors (FETs) with channel widths down to 20 nm have been fabricated by a conventional…
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Highly Cited
2003
Highly Cited
2003
Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs
J. Colinge
,
J. Park
,
W. Xiong
IEEE Electron Device Letters
2003
Corpus ID: 28286589
The subthreshold swing and threshold voltage characteristics of multiple-gate SOI transistors have been numerically simulated…
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Highly Cited
1998
Highly Cited
1998
25 nm CMOS design considerations
Y. Taur
,
C. Wann
,
David J. Frank
International Electron Devices Meeting…
1998
Corpus ID: 29825196
This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS…
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Highly Cited
1987
Highly Cited
1987
An SOI voltage-controlled bipolar-MOS device
J. Colinge
IEEE Transactions on Electron Devices
1987
Corpus ID: 27821772
This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI…
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Highly Cited
1987
Highly Cited
1987
Hot-electron effects in Silicon-on-insulator n-channel MOSFET's
J. Colinge
IEEE Transactions on Electron Devices
1987
Corpus ID: 41702799
Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the…
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Highly Cited
1983
Highly Cited
1983
Effects of grain boundaries on the channel conductance of SOl MOSFET's
J. Fossum
,
A. Ortiz-Conde
IEEE Transactions on Electron Devices
1983
Corpus ID: 40934824
A physical model that describes the effects of grain boundaries on the linear-region (strong-inversion) channel conductance of…
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