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Signoff (electronic design automation)

Known as: Signoff (EDA) 
In the automated design of integrated circuits, signoff (also written as sign-off) checks is the collective name given to a series of verification… Expand
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Related topics

Related topics

18 relations
Application-specific integrated circuitElectromigrationElectronic design automationFormal verification
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Efficient Timing Closure in SOC through Timing Quality Checks and Engineering Change Order
Ensuring correct operation of design despite rising levels of design complexity has been a major focus of research and… Expand
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2017
2017
Incremental Layer Assignment Driven by an External Signoff Timing Engine
Modern technologies provide wide and thick metal layers that must be wisely used to reduce the delay of critical interconnections… Expand
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2014
2014
On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling
Transistor aging due to bias temperature instability (BTI) is a major reliability concern in sub-32 nm technology. To compensate… Expand
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2014
2014
Improved signoff methodology with tightened BEOL corners
To ensure functional correctness, conventional chip implementation methodology signs off the SOC design at extreme process… Expand
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2013
2013
Impact of adaptive voltage scaling on aging-aware signoff
Transistor aging due to bias temperature instability (BTI) is a major reliability concern in sub-32nm technology. Aging decreases… Expand
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2013
2013
Learning-based approximation of interconnect delay and slew in signoff timing tools
Incremental static timing analysis (iSTA) is the backbone of iterative sizing and Vt-swapping heuristics for post-layout timing… Expand
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2013
2013
Optimization of overdrive signoff
In modern SOC implementations, multi-mode design is commonly used to achieve better circuit performance and power across voltage… Expand
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2011
2011
The Future of Signoff
This column examines the challenges inherent in the signoff stage of the design cycle just prior to fabrication. Modeling trends… Expand
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2008
2008
Practical Clock Tree Robustness Signoff Metrics
Clock tree analysis and signoff is a key step in the design of any high performance chip. Though simple and intutive metrics like… Expand
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2006
2006
A comprehensive solution for true hierarchical timing and crosstalk delay signoff
Leading edge technology advancements have posed big challenges for the digital design flow. Designing multi-million gate ICs at… Expand
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