Signoff (electronic design automation)

Known as: Signoff (EDA) 
In the automated design of integrated circuits, signoff (also written as sign-off) checks is the collective name given to a series of verification… (More)
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Topic mentions per year

Topic mentions per year

2003-2017
02420032017

Papers overview

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2015
2015
In advanced technology nodes, incremental delay due to coupling is a serious concern. Design companies spend significant… (More)
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2014
2014
Signoff timing analysis remains a critical element in the IC design flow. Multiple signoff corners, libraries, design… (More)
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2014
2014
Monolithic 3D ICs (M3D) are an emerging technology that offers an ultra-high-density 3D integration due to the extremely small… (More)
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2014
2014
PDN evaluation/synthesis techniques have been used to facilitate the planning/construction of PDNs in integrated circuits at… (More)
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2013
2013
In modern SOC implementations, multi-mode design is commonly used to achieve better circuit performance and power across voltage… (More)
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2011
2011
‘‘SIGNOFF’’ IS A near-magical word. It connotes a design state that is with respect to the designer’s functional constraints and… (More)
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2009
2009
With shrinking geometries and increasing complexity of the designs, the use of SPICE simulator (SPICE) is a must to perform… (More)
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2008
2008
Clock tree analysis and signoff is a key step in the design of any high performance chip. Though simple and intutive metrics like… (More)
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Review
2007
Review
2007
Power management for contactless smartcards (SC) is mandatory since energy is supplied by RF electromagnetic waves. At any time… (More)
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2006
2006
Leading edge technology advancements have posed big challenges for the digital design flow. Designing multi-million gate ICs at… (More)
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