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Semiconductor intellectual property core
Known as:
IP Core
, Logic core
, IP
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In electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or chip layout design that…
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Related topics
Related topics
50 relations
AC'97
AMD Radeon Crimson
AMD Radeon Rx 200 series
ARM architecture
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Broader (1)
Electronic design automation
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Improving FPGA Performance for Carry-Save Arithmetic
H. Parandeh-Afshar
,
A. K. Verma
,
P. Brisk
,
P. Ienne
IEEE Transactions on Very Large Scale Integration…
2010
Corpus ID: 8460464
The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry…
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Highly Cited
2008
Highly Cited
2008
A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment
Timo Vogt
,
N. Wehn
IEEE Transactions on Very Large Scale Integration…
2008
Corpus ID: 26434988
Future mobile and wireless communication networks require flexible modem architectures to support seamless services between…
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Highly Cited
2007
Highly Cited
2007
A Fast Mode Decision Algorithm and Its VLSI Design for H.264/AVC Intra-Prediction
Jia-Ching Wang
,
Jhing-Fa Wang
,
J. Yang
,
Jang-Ting Chen
IEEE transactions on circuits and systems for…
2007
Corpus ID: 10884869
In this paper, we present a fast mode decision algorithm and design its VLSI architecture for H.264 intra-prediction. A regular…
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2007
2007
Multilevel MPSOC simulation using an MDE approach
R. B. Atitallah
,
Éric Piel
,
S. Niar
,
P. Marquet
,
J. Dekeyser
IEEE International SOC Conference
2007
Corpus ID: 8469795
In this paper, we first present an efficient Multi-Processor Systems-on-Chip design methodology based on Model-Driven Engineering…
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2005
2005
A high-performance architecture for embedded block coding in JPEG 2000
G. Pastuszak
IEEE transactions on circuits and systems for…
2005
Corpus ID: 38936433
JPEG 2000 offers critical advantages over other still image compression schemes at the price of increased computational…
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2005
2005
Toward a processor core for real-time capable autonomic systems
S. Uhrig
,
S. Maier
,
T. Ungerer
Proceedings of the Fifth IEEE International…
2005
Corpus ID: 14351243
This paper proposes a processor core that allows to support the autonomic computing principles in embedded hard-real-time systems…
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2004
2004
A low-power DCT IP core based on 2D algebraic integer encoding
Minyi Fu
,
G. Jullien
,
V. Dimitrov
,
M. Ahmadi
IEEE International Symposium on Circuits and…
2004
Corpus ID: 34648543
This paper discusses the application of a new two dimensional algebraic integer encoding scheme for the design of a DCT processor…
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Highly Cited
2002
Highly Cited
2002
Embedded timing analysis: a soc infrastructure
S. Tabatabaei
,
A. Ivanov
IEEE Design & Test of Computers
2002
Corpus ID: 23219114
This SoC infrastructure core is a flexible, scalable, and highly accurate embedded time interval analyzer (ETIA), used to measure…
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2002
2002
Presentation of an efficient design methodology for FPGA implementation of control systems. Application to the design of an antiwindup PI controller
L. Charaabi
,
E. Monmasson
,
I. Slama-Belkhodja
IEEE 28th Annual Conference of the Industrial…
2002
Corpus ID: 62963887
This paper presents an efficient design methodology to develop IP-core functions in VHDL for control systems. This methodology is…
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Highly Cited
1999
Highly Cited
1999
Verifying IP-core based system-on-chip designs
Pankay Chauhan
,
E. Clarke
,
Yuan Lu
,
D. Wang
Twelfth Annual IEEE International ASIC/SOC…
1999
Corpus ID: 11406451
We describe a methodology for verifying system-on-chip designs. In our methodology, the problem of verifying system-on-chip…
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