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Segmented scan

In computer science a segmented scan is modification of a prefix sum with an equal sized array of flag bits to denote segment boundaries on which the… 
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Computer sciencePrefix sum

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Efficient Transactional-Memory-based Implementation of Morph Algorithms on GPU
General Purpose GPUs (GPGPUs) are ideal platforms for parallel execution of applications with regular shared memory access… 
2017
2017
Frequency scaled segmented (FSS) scan architecture for optimized scan-shift power and faster test application time
Scan shift power consumption is one of the major concerns in low power circuits. While there are multiple design for testability… 
2015
2015
A new decompressor with ordered parallel scan design for reduction of test data and test time
Scan design is regarded as the best design-for-testability (DfT) discipline. High test data volume and long test time are always… 
Highly Cited
2011
Highly Cited
2011
Efficient Parallel Scan Algorithms for GPUs
Scan and segmented scan algorithms are crucial building blocks for a great many data-parallel algorithms. Segmented scan and… 
2011
2011
‘misspelled’ visual words in unsupervised range data classification: the effect of noise on classification performance
Recent work in the domain of classification of point clouds has shown that topic models can be suitable tools for inferring class… 
2008
2008
Segmented scan architecture using segment grouping for test cost reduction
This paper presents a segmented scan architecture to reduce both test application time and test power consumption. The proposed… 
Highly Cited
2008
Highly Cited
2008
Fast scan algorithms on graphics processors
Scan and segmented scan are important data-parallel primitives for a wide range of applications. We present fast, work-efficient… 
2006
2006
Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction
This paper presents multi-mode segmented scan architecture. Three operation modes are supported: broadcast, multicast, and serial… 
2004
2004
Time and work optimal simulation of basic reconfigurable meshes on hypercubes
1988
1988
Efficient scan operators for bit-serial processor arrays
A fast algorithm is presented for broadcasting a word of length w on an n*n single-instruction multiple-data (SIMD) array of bit… 
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