Po-Chang Tsai

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In this paper, we proposed a test data compression scheme targeted for minimizing the amount of test data. The proposed scheme can reduce the test application time and minimize the amount of compressed test data, which reduces the size of data memory in ATE and the time needed to transfer test data. A decoder design is also presented. Experimental results(More)
We propose a structured design methodology to construct FSM-based programmable memory BIST. The proposed BIST can be programmed on-line, with a " macro command " , to select a test algorithm from a predetermined set of algorithms that are built in the memory BIST. In general, there are a variety of heterogeneous memory modules in SOC, and it is not possible(More)
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