SPARC

Known as: Sun Sparc, SPARC International, Sparc 32 
The Scalable Processor Architecture (SPARC) is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by… (More)
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Topic mentions per year

1971-2018
020406019712018

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2014
2014
This article consists of a collection of slides from the author's conference presentation on the special features, system design… (More)
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2011
Highly Cited
2011
The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly… (More)
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2009
Highly Cited
2009
Rock, Sun's third-generation chip-multithreading processor, contains 16 high-performance cores, each of which can support two… (More)
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Highly Cited
2007
Highly Cited
2007
UltraSPARC T2 is Sun Microsystems' second generation multi-core, multi-threaded SPARC System-on-a-chip. It delivers twice the… (More)
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Highly Cited
2007
Highly Cited
2007
The 8-core 64-thread 64b power-efficient 2nd-generation Niagara SPARC SoC has 4MB L2 cache with one times8 PCI-Express, two 10G… (More)
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2006
Highly Cited
2006
This first generation of "Niagara" SPARC processors implements a power-efficient Chip Multi-Threading (CMT) architecture which… (More)
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2005
Highly Cited
2005
The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server… (More)
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2005
Highly Cited
2005
We present the internals of QEMU, a fast machine emulator using an original portable dynamic translator. It emulates several CPUs… (More)
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2002
Highly Cited
2002
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on… (More)
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1996
1996
This paper presents a multithreaded processor, the MSparc. MSparc supports up to four contexts on chip and employs block mul… (More)
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