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SPARC

Known as: Sun Sparc, SPARC International, SPARC (disambiguation) 
The Scalable Processor Architecture (SPARC) is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by… 
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Related topics

Related topics

50 relations
32-bitAfara WebsystemsBerkeley RISCBit numbering

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Adaptive data-aware utility-based scheduling in resource-constrained systems
2008
2008
The energy cost of SSL in deeply embedded systems
As the number of potential applications for tiny, battery-powered, "mote"-like, deeply embedded devices grows, so does the need… 
2002
2002
Migration velocity analysis from locally coherent events in 2-D laterally heterogeneous media, Part II: Applications on synthetic and real data
We demonstrate a method for estimating 2-D velocity models from synthetic and real seismic reflection data in the framework of… 
2002
2002
The Sun Fireplane Interconnect
A computing system's internal interconnect is a key determiner of its cost, performance, and reliability. The Sun Fireplane… 
2000
2000
Mixed-mode Bytecode Execution
Modern high-performance virtual machines use dynamic compilation. There is a tension between compilation speed and code quality… 
2000
2000
Memory Access Schemes for Configurable Processors
This work discusses the Memory Architecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface… 
Highly Cited
1997
Highly Cited
1997
QSPR as a means of predicting and understanding chemical and physical properties in terms of structure
Abstract 
1997
1997
Toward a Scalable Distributed {WWW} Server on Workstation Clusters
In this paper, we investigate the issues involved in developing a scalable World Wide Web (WWW) server called SWEB on a cluster… 
1994
1994
Concurrent error-detection and modular fault-tolerance in a 32-bit processing core for embedded space flight applications
  • J. Gaisler
  • Proceedings of IEEE 24th International Symposium…
  • 1994
  • Corpus ID: 15293777
This paper describes the concurrent error-detection methods employed in the ERC32, a 32-bit processing core for embedded space… 
Highly Cited
1993
Highly Cited
1993
PHI - A Logic-Based Tool for Intelligent Help Systems
We introduce a logic-based system which improves the performance of intelligent help systems by supplying them with plan… 
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