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Register renaming
Known as:
Issue queue
, Remap file
In computer architecture, register renaming is a technique that eliminates the false data dependencies arising from the reuse of architectural…
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Related topics
Related topics
46 relations
AMD K5
Address generation unit
Athlon
Belt machine
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation
F. Pouyan
,
A. Azarpeyvand
,
S. Safari
,
S. M. Fakhraie
IET Computers & Digital Techniques
2015
Corpus ID: 29296683
Miniaturisation in modern microprocessors increases susceptibility to soft errors leading to reliability degradation. Recently…
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2011
2011
A Tableaux Based Decision Procedure for a Broad Class of Hybrid Formulae with Binders
S. Cerrito
,
M. C. Mayer
International Conference on Theorem Proving with…
2011
Corpus ID: 14263379
In this paper we provide the first (as far as we know) direct calculus deciding satisfiability of formulae in negation normal…
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2010
2010
Modeling and Implementation of Threshold Logic Circuits and Architectures
S. Leshner
2010
Corpus ID: 61530128
Threshold logic has long been studied as a means of achieving higher performance and lower power dissipation, providing…
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2010
2010
Non-speculative enhancements for the scheduling logic
Rubén Gran Tejero
2010
Corpus ID: 209072296
This thesis focuses on a tradeoff between desirable objectives in High-Performance Out-of-Order processors. In particular, we…
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2009
2009
Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming
Kaveh Aasaraai
,
Andreas Moshovos
International Conference on Field-Programmable…
2009
Corpus ID: 2749429
As a step torward a viable, single-issue out-of-order soft core, this work presents Copy-Free Checkpointing (CFC), an FPGA…
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2007
2007
Asymmetrically Banked Value-Aware Register Files
Shuai Wang
,
Hongyan Yang
,
Jie S. Hu
,
Sotirios G. Ziavras
IEEE Computer Society Annual Symposium on VLSI
2007
Corpus ID: 7383154
Designing high-performance low-power register files is of critical importance to the continuation of current performance advances…
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2005
2005
2L-MuRR: A Compact Register Renaming Scheme for SMT Processors
Hua Yang
,
G. Cui
,
Xiaozong Yang
International Symposium on Image and Signal…
2005
Corpus ID: 45465292
In simultaneous multithreaded (SMT) processors, a larger multi-ported rename register file is indispensable for holding more…
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2004
2004
Leakage energy reduction in register renaming
Masaharu Goto
,
Toshinori Sato
24th International Conference on Distributed…
2004
Corpus ID: 37506276
Register files are becoming a power-hungry component in future embedded microprocessors, as a lot of power reduction techniques…
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2002
2002
Complexity-Effective Issue Queue Design Under Load-Hit Speculation
T. Moreshet
,
R. I. Bahar
2002
Corpus ID: 16483501
Current trends in microprocessor designs indicate increasing pipeline depth in order to keep up with higher clock frequencies and…
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2000
2000
Scalable Register Renaming via the Quack Register File
Bryan Black
,
John Paul Shen
2000
Corpus ID: 59725849
To improve the performance of superscalar microprocessors, developers are continually deepening pipelines, increasing the…
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