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Register renaming
Known as:
Issue queue
, Remap file
In computer architecture, register renaming is a technique that eliminates the false data dependencies arising from the reuse of architectural…
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Related topics
Related topics
46 relations
AMD K5
Address generation unit
Athlon
Belt machine
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
A multiported register file with register renaming for configurable softcore VLIW processors
Fakhar Anjam
,
Stephan Wong
,
F. Nadeem
International Conference on Field-Programmable…
2010
Corpus ID: 1726879
In this paper, we present the design and implementation of a BRAM-based multiported register file with arbitrary number of read…
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2006
2006
Static program analysis based on virtual register renaming
Jeremy Singer
2006
Corpus ID: 14334741
Static single assignment form (SSA) is a popular program intermediate representation (IR) for static analysis. SSA programs…
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Highly Cited
2003
Highly Cited
2003
Front-end policies for improved issue efficiency in SMT processors
A. El-Moursy
,
D. Albonesi
The Ninth International Symposium on High…
2003
Corpus ID: 370196
The performance and power optimization of dynamic superscalar microprocessors requires striking a careful balance between…
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Highly Cited
2001
Highly Cited
2001
Random Register Renaming to Foil DPA
D. May
,
H. Muller
,
N. Smart
Workshop on Cryptographic Hardware and Embedded…
2001
Corpus ID: 9738631
Techniques such as DPA and SPA can be used to find the secret keys stored in smart-cards. These techniques have caused concern…
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Highly Cited
2001
Highly Cited
2001
A circuit level implementation of an adaptive issue queue for power-aware microprocessors
A. Buyuktosunoglu
,
D. Albonesi
,
S. Schuster
,
D. Brooks
,
P. Bose
,
P. Cook
ACM Great Lakes Symposium on VLSI
2001
Corpus ID: 2521753
Increasing power dissipation has become a major constraint for future performance gains in the design of microproces sors In this…
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Highly Cited
2001
Highly Cited
2001
Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources
D. Ponomarev
,
Gürhan Küçük
,
K. Ghose
Proceedings. 34th ACM/IEEE International…
2001
Corpus ID: 570210
The "one-size-fits-all" philosophy used for permanently allocating datapath resources in today's superscalar CPUs to maximize…
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Highly Cited
2001
Highly Cited
2001
Inherently Lower-Power High-Performance Superscalar Architectures
V. Zyuban
,
P. Kogge
IEEE Trans. Computers
2001
Corpus ID: 35334947
In recent years, reducing power has become an important design goal for high-performance microprocessors. This work attempts to…
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2000
2000
Scalable Register Renaming via the Quack Register File
B. Black
,
John Paul Shen
2000
Corpus ID: 59725849
To improve the performance of superscalar microprocessors, developers are continually deepening pipelines, increasing the…
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1999
1999
The design of a register renaming unit
B. Bishop
,
T. Kelliher
,
M. J. Irwin
Proceedings Ninth Great Lakes Symposium on VLSI
1999
Corpus ID: 15160737
Register renaming is often used to improve performance in many high-ILP processors. However there is a lack of publications…
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Highly Cited
1996
Highly Cited
1996
Register file design considerations in dynamically scheduled processors
K. Farkas
,
N. Jouppi
,
P. Chow
Proceedings. Second International Symposium on…
1996
Corpus ID: 14344496
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch…
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