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Register renaming
Known as:
Issue queue
, Remap file
In computer architecture, register renaming is a technique that eliminates the false data dependencies arising from the reuse of architectural…
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AMD K5
Address generation unit
Athlon
Belt machine
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
A Novel Register Renaming Technique for Out-of-Order Processors
Hamid Tabani
,
J. Arnau
,
Jordi Tubella
,
Antonio González
International Symposium on High-Performance…
2018
Corpus ID: 4570485
Modern superscalar processors support a large number of in-flight instructions, which requires sizeable register files…
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2010
2010
Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays
Taniya Siddiqua
,
S. Gurumurthi
IEEE Computer Society Annual Symposium on VLSI
2010
Corpus ID: 16413317
Negative Bias Temperature Instability (NBTI) is an important lifetime reliability problem in microprocessors. SRAM-based…
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2010
2010
A multiported register file with register renaming for configurable softcore VLIW processors
Fakhar Anjam
,
Stephan Wong
,
F. Nadeem
International Conference on Field-Programmable…
2010
Corpus ID: 1726879
In this paper, we present the design and implementation of a BRAM-based multiported register file with arbitrary number of read…
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2010
2010
BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution
Andrew D. Hilton
,
A. Roth
International Symposium on High-Performance…
2010
Corpus ID: 3249177
LT (latency tolerant) execution is an attractive candidate technique for future out-of-order cores. LT defers the forward slices…
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2008
2008
Towards distributed storage resource management using flow control
Ajay Gulati
,
I. Ahmad
OPSR
2008
Corpus ID: 7436563
Deployment of shared storage systems is increasing with rapid adoption of virtualization technologies to provide flexible sharing…
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2005
2005
Instruction packing: reducing power and delay of the dynamic scheduling logic
J. Sharkey
,
D. Ponomarev
,
K. Ghose
,
Oğuz Ergin
ISLPED '05. Proceedings of the International…
2005
Corpus ID: 1972443
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue…
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2003
2003
Energy Efficient Register Renaming
Gürhan Küçük
,
Oğuz Ergin
,
D. Ponomarev
,
K. Ghose
International Workshop on Power and Timing…
2003
Corpus ID: 28825927
Modern microprocessor designs implement register renaming using register alias tables (RATs), which maintain the mapping between…
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2002
2002
AccuPower: an accurate power estimation tool for superscalar microprocessors
D. Ponomarev
,
Gürhan Küçük
,
K. Ghose
Proceedings Design, Automation and Test in…
2002
Corpus ID: 1251933
This paper describes the AccuPower toolset-a set of simulation tools accurately estimating the power dissipation within a…
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2000
2000
Scalable Register Renaming via the Quack Register File
B. Black
,
John Paul Shen
2000
Corpus ID: 59725849
To improve the performance of superscalar microprocessors, developers are continually deepening pipelines, increasing the…
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1999
1999
The design of a register renaming unit
B. Bishop
,
T. Kelliher
,
M. J. Irwin
Proceedings Ninth Great Lakes Symposium on VLSI
1999
Corpus ID: 15160737
Register renaming is often used to improve performance in many high-ILP processors. However there is a lack of publications…
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