Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 225,836,033 papers from all fields of science
Search
Sign In
Create Free Account
Register file
Known as:
RF (disambiguation)
A register file is an array of processor registers in a central processing unit (CPU). Modern integrated circuit-based register files are usually…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
50 relations
AMD K6
ARM architecture
Alpha 21064
Atmel AVR
Expand
Broader (2)
Computer architecture
Digital electronics
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2009
2009
An Embedded Stream Processor Core Based on Logarithmic Arithmetic for a Low-Power 3-D Graphics SoC
Byeong-Gyu Nam
,
H. Yoo
IEEE Journal of Solid-State Circuits
2009
Corpus ID: 14957769
A low-power and high-performance 4-way 32-bit stream processor core is developed for handheld low-power 3-D graphics systems. It…
Expand
Highly Cited
2005
Highly Cited
2005
A Lower-Power Register File Based on Complementary Pass-Transistor Adiabatic Logic
Jianping Hu
,
Tiefeng Xu
,
Hong Li
IEICE Trans. Inf. Syst.
2005
Corpus ID: 9664023
This paper presents a novel low-power register file based on adiabatic logic. The register file consists of a storage-cell array…
Expand
2004
2004
A Massively Multithreaded Packet Processor
S. Melvin
,
M. Nemirovsky
,
+4 authors
Koroush A. Saraf
2004
Corpus ID: 8630527
Highly Cited
2003
Highly Cited
2003
Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264
Tu-Chih Wang
,
Yu-Wen Huang
,
Hung-Chi Fang
,
Liang-Gee Chen
Proceedings of the International Symposium on…
2003
Corpus ID: 4212838
Transform coding has been widely used in video coding standards. In this paper, a hardware architecture for accelerating…
Expand
2002
2002
Loop fusion for clustered VLIW architectures
Yi Qian
,
S. Carr
,
P. Sweany
LCTES/SCOPES '02
2002
Corpus ID: 2340341
Embedded systems require maximum performance from a processor within significant constraints in power consumption and chip cost…
Expand
2000
2000
Improved spill code generation for software pipelined loops
J. Zalamea
,
J. Llosa
,
E. Ayguadé
,
M. Valero
ACM-SIGPLAN Symposium on Programming Language…
2000
Corpus ID: 11632589
Software pipelining is a loop scheduling technique that extractsparallelism out of loops by overlapping the execution of…
Expand
Highly Cited
1998
Highly Cited
1998
Clustered Instruction-Level Parallel Processors
P. Faraboschi
,
G. Desoli
,
+12 authors
Iloh Ehfrphv
1998
Corpus ID: 208911306
VLIW, registers, clustering, compilers, EPIC, scheduling CPUs with a large amount of instruction-level parallelism must carry out…
Expand
Highly Cited
1994
Highly Cited
1994
An integrated approach to retargetable code generation
T. C. Wilson
,
G. Grewal
,
B. Halley
,
D. Banerji
Proceedings of 7th International Symposium on…
1994
Corpus ID: 14384424
Special-purpose instruction set processors (ISPs) challenge compilers because of instruction level parallelism, small numbers of…
Expand
1993
1993
Speculative execution exception recovery using write-back suppression
Roger A. Bringmann
,
S. Mahlke
,
R. Hank
,
J. Gyllenhaal
,
Wen-mei W. Hwu
Proceedings of the 26th Annual International…
1993
Corpus ID: 3566845
One of the key design concerns of multiple instruction issue (MII) processors is deciding how many memory ports need to be…
Expand
1964
1964
Serial-to-Parallel Transformation of Linear-Feedback Shift-Register Circuits
M. Hsiao
,
K. Sih
IEEE Transactions on Electronic Computers
1964
Corpus ID: 206506957
Linear-feedback shift-register circuits have been studied extenOE--Exclusive OR Gate sively.'-' These studies concentrated mainly…
Expand
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE