A redundant binary representation (RBR) is a numeral system that uses more bits than needed to represent a single binary digit so that most numbersâ€¦Â (More)

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2014

2014

- A. A. El-Slehdar, A. H. Fouad, Ahmed Gomaa Radwan
- 2014 International Conference on Engineering andâ€¦
- 2014

This paper introduces a memristor based redundant binary adder for canonic signed digit code, that coding eliminates the carryâ€¦Â (More)

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2009

2009

- Yajuan He, Chip Hong Chang
- IEEE Transactions on Circuits and Systems Iâ€¦
- 2009

The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its highâ€¦Â (More)

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2008

2008

- Yajuan He, Chip Hong Chang
- IEEE Transactions on Circuits and Systems Iâ€¦
- 2008

This paper presents an efficient reverse converter for transforming the redundant binary (RB) representation into two'sâ€¦Â (More)

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2005

2005

- Yajuan He, Chip Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy
- 2005 IEEE International Symposium on Circuits andâ€¦
- 2005

The benefit of high radix Booth encoders in reducing the number of partial products in fast multipliers has been hampered by theâ€¦Â (More)

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2004

2004

- Chip Hong Chang, Yajuan He, Jiangmin Gu
- The 2004 IEEE Asia-Pacific Conference on Circuitsâ€¦
- 2004

This work addresses the feasibility of re-engineering the multiplier architecture that is based on a new redundant numberâ€¦Â (More)

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1989

1989

- Sau-Gee Chen
- Eighth Annual International Phoenix Conference onâ€¦
- 1989

An addition rule for signed-digit representation (SDR), generalized from the addition rule of redundant binary representation, isâ€¦Â (More)

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1987

1987

- Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi
- 1987 IEEE 8th Symposium on Computer Arithmeticâ€¦
- 1987

A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and theâ€¦Â (More)

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1987

1987

- Naofumi Takagi, Shuzo Yajima
- IEEE Transactions on Computers
- 1987

An on-line error-detectable high-speed multiplier is described. It is based on the multiplication algorithm which we haveâ€¦Â (More)

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1986

1986

- Naofumi Takagi, Shuzo Yajima
- Systems and Computers in Japan
- 1986

In this paper, we propose hardware algorithms for computing exponentials and logarithms utilizing the redundant binaryâ€¦Â (More)

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Highly Cited

1985

Highly Cited

1985

- Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima
- IEEE Transactions on Computers
- 1985

A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integerâ€¦Â (More)

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