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Redundant binary representation

Known as: Redundant Binary 
A redundant binary representation (RBR) is a numeral system that uses more bits than needed to represent a single binary digit so that most numbers… 
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Related topics

Related topics

10 relations
AND gateArithmetic logic unitBinary numberBitwise operation

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation
Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC… 
2004
2004
A unified unsigned/signed binary multiplier
  • Guoping Wang
  • Conference Record of the Thirty-Eighth Asilomar…
  • 2004
  • Corpus ID: 43994723
Multiplication is a very important operation in digital computing systems. Both signed and unsigned multiplications are required… 
2002
2002
High-performance divider using redundant binary representation
A high-performance iterative quadratic convergence fixed-point, real and complex number, divider circuit using a previously… 
2002
2002
Design of a high-speed RSA encryption processor based on the residue table for redundant binary numbers
The RSA cryptosystem plays an important role in ensuring the security of network communications, although it has the drawback… 
2001
2001
The implementation of an efficient and high-speed inner-product processor
A novel, high-performance fixed-point inner-product processor based on a redundant binary number system is presented. The… 
1997
1997
Recoders for Partial Compression and Rounding
The purpose of this paper is to treat digit set conversions and digit recodings in terms of primitive recoding operations that… 
1994
1994
Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation
Proposes a new algorithm of estimation and compensation of the error effect for rounding in the case of implementation of… 
1994
1994
A 10 bit 20 MS/s 3 V supply CMOS A/D converter
A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI's. In this A/D… 
1993
1993
A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture
A new redundant binary (RB) architecture for a high-speed multiplier is presented. In this architecture, a pair of partial… 
Highly Cited
1988
Highly Cited
1988
A 33 Mflops Floating Point Processor Using Redundant Binary Representation
A 33MFLOPS single precision floating point processor that uses the redundant binary representation in a multiplier (FMUL) and a… 
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