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Quad data rate
Known as:
QDR
, Quad-pumped
, Quadruple data rate
Quad data rate (QDR, or quad pumping) is a communication signaling technique wherein data are transmitted at four points in the clock cycle: on the…
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Related topics
Related topics
7 relations
Central processing unit
Clock rate
Double data rate
List of Intel chipsets
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Broader (1)
Digital electronics
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach
Priyanka Chauhan
,
Dippal Israni
,
Karan Jasani
,
Ashwin Makwana
International journal of engineering and…
2018
Corpus ID: 70086552
Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data…
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2015
2015
JURECA: Jülich Research on Exascale Cluster Architectures
Dorian Krause
2015
Corpus ID: 195961501
Spring 2015 • Vol. 13 No. 1 • inSiDE According to its dual architecture strategy, Forschungszentrum Jülich is offering access to…
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2015
2015
Throughput studies on an InfiniBand interconnect via all-to-all communications
Nil Mistry
,
J. Ramsey
,
Benjamin Wiley
,
Jackie Yanchuck
,
Xuan Huang
,
M. Gobbert
Spring Simulation Multiconference
2015
Corpus ID: 16598042
Distributed-memory clusters are the most important type of parallel computer today, and they dominate the TOP500 list. The…
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2013
2013
ESTIMATION OF NOISE FIGURE USING GFF WITH HYBRID QUAD PUMPING
V. R. Prakash
,
Himanshu Shekhar
,
P. Diderot
2013
Corpus ID: 107866966
This Paper describes the models and simulation of EDFA(Erbium Doped Fiber Amplifier) with optimized Gain and that has been…
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2013
2013
An Implementation of Binomial Method of Option Pricing using Parallel Computing
Sai K. Popuri
,
Andrew M. Raim
,
N. Neerchal
,
M. Gobbert
2013
Corpus ID: 15462683
The Binomial method of option pricing is based on iterating over discounted option payoffs in a recursive fashion to calculate…
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2012
2012
The Graph 500 Benchmark on a Medium-Size Distributed-Memory Cluster with High-Performance Interconnect
Jordan Angel
,
A. M. Flores
,
+4 authors
D. Mountain
2012
Corpus ID: 61512503
While traditional performance benchmarks for high-performance computers measure the speed of arithmetic operations, memory access…
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2001
2001
A redundant multi-valued logic for 10 Gb/s CMOS demultiplexer IC
A. Tanabe
,
Y. Nakahara
,
A. Furukawa
,
T. Mogami
IEEE International Solid-State Circuits…
2001
Corpus ID: 26514478
A redundant multi-valued logic is used in >Gb/s communication lC applications. Using this logic, a quadruple data rate…
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2000
2000
A 500 Mb/s/pin quadruple data rate SDRAM interface using a skew cancellation technique
Jeongpyo Kim
,
Joonsuk Lee
,
+7 authors
Beomsup Kim
IEEE International Solid-State Circuits…
2000
Corpus ID: 24377701
The operating speed of microprocessors has become faster than 500 MHz, while memory access speed has not been improved…
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2000
2000
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique
Sung-Ho Wang
,
Jeongpyo Kim
,
+8 authors
Beomsup Kim
IEEE J. Solid State Circuits
2000
Corpus ID: 61205246
The operating speed of microprocessors has become faster than 500 MHz, while memory access speed has not been improved…
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2000
2000
Method of drive word line and bit line for read and write in quad data rate synchronous sram and circuit of thereof
김민규
2000
Corpus ID: 108346783
PURPOSE: A method and a circuit for driving a bit line and a word line for read/write of quad data rate are provided to enable…
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