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Prescaler Device Component

Known as: Prescaler 
An electronic counter device designed to reduce a very high frequency signal to a lower frequency by division.
National Institutes of Health

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Medical Device Component or Accessory

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2006
2006
On the conception and analysis of a 12-GHz push-push phase-locked DRO
This paper describes the design and behavior of a 12-GHz push-push dielectric resonator oscillator in a phase-locked environment… 
2005
2005
A new integrated monocycle generator and transmitter for ultra-wideband (UWB) communications
In this paper, we propose a gated pulse generator incorporating two modulation schemes for use in an ultra-wideband impulse radio… 
2004
2004
A 1-V 5.2-GHz CMOS synthesizer for WLAN applications
A 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented. Novel circuit designs are demonstrated in the system for… 
2003
2003
A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free
SUMMARY A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip… 
2001
2001
A W-CDMA zero-IF front-end for UMTS in a 75 GHz SiGe BiCMOS technology
A zero-IF front-end consisting of an I/Q down-conversion mixer, broadband I/Q-generation, fully-integrated VCO, dual-modulus… 
2000
2000
A 900-MHz 1-V CMOS frequency synthesizer
A 900-MHz 1-V frequency synthesizer has been fabricated in a standard 0.35-/spl mu/m CMOS technology. The frequency synthesizer… 
1999
1999
A quarter-micron CMOS, 1 GHz VCO/prescaler-set for very low power applications
A VCO and a prescaler designed for wireless applications with very low power consumption requirements are presented. The VCO has… 
1998
1998
A 1.57-GHz RF front-end for triple conversion GPS receiver
A low-power, 1.57 GHz RF front-end for a Global Positioning System (GPS) receiver has been designed in a 1.0 /spl mu/m BiCMOS… 
1994
1994
1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2 /spl mu/m CMOS prescalers
We have implemented a dual-modulus prescaler dividing either by 64/65 (128/129) in a 1.2 /spl mu/m standard CMOS process. Using… 
1994
1994
A 1.2 /spl mu/m CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer
A single-chip, low-power all CMOS PLL frequency synthesizer for digital mobile radio communication systems is presented. The… 
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