Kyoung-Rok Cho

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Large-capacity content addressable memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more years.(More)
This paper presents a motion compensated frame rate up-conversion algorithm that uses the expanded range of the motion trajectory to enhance the accuracy of motion estimation. In the proposed algorithm, an adaptive motion vector refinement is also proposed to correct false motion vectors. In addition, a recursive motion vector smoothing is proposed to(More)
The nonvolatile memory property of a memristor enables the realization of new methods for a variety of computational engines ranging from innovative memristive-based neuromorphic circuitry through to advanced memory applications. The nanometer-scale feature of the device creates a new opportunity for realization of innovative circuits that in some cases are(More)
As conventional memory technologies are challenged by their technological physical limits, emerging technologies driven by novel materials are becoming an attractive option for future memory architectures. Among these technologies, Resistive Memories (ReRAM) created new possibilities because of their nanofeatures and unique <i>I</i>-<i>V</i>(More)
This brief describes a new linear operational transconductance amplifier (OTA) and its application to a ninth-order Bessel filter. To improve the linearity of the OTA, we employ a mobility compensation circuit which combines the transistors operating in the triode and the subthreshold regions. The proposed technique enhances the linearity of the(More)
This paper proposes a new SHA-1 architecture to exploit higher parallelism and to shorten the critical path for Hash operations. It enhances a performance without significant area penalty. We implemented the proposed SHA-1 architecture on FPGA that showed the maximum clock frequency of 118MHz allows a data throughput rate of 5.9Gbps. The throughput is about(More)
We present new computational building blocks based on memristive devices. These blocks, can be used to implement either supervised or unsupervised learning modules. This is achieved using a crosspoint architecture which is an efficient array implementation for nanoscale two-terminal mem-ristive devices. Based on these blocks and an experimentally verified(More)