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Plesiochronous system

Known as: Plesiochrony, Plesiochronous difference, Plesiochronous 
In telecommunications, a plesiochronous system is one where different parts of the system are almost, but not quite, perfectly synchronised… 
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Related topics

Related topics

9 relations
Asynchronous serial communicationAsynchronous systemClock driftMesochronous network

Broader (1)

Network architecture

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2020
2020
PALS: Plesiochronous and Locally Synchronous Systems
Consider an arbitrary network of communicating modules on a chip, each requiring a local signal telling it when to execute a… 
Highly Cited
2009
Highly Cited
2009
A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS
This paper presents a quarter-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O-links. The 2times… 
2008
2008
5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS
This paper presents a quarter rate clock/data recovery (CDR) circuit for plesiochronous serial I/O-links. This 2x-oversampled… 
Review
2006
Review
2006
VCAT-LCAS in a clamshell
Virtual concatenation (VCAT) is a standardized layer 1 inverse multiplexing technique that can be applied to the optical… 
Highly Cited
2003
Highly Cited
2003
Timing measurements of synchronization circuits
A regular (two-flop) synchronizer and six multi-synchronous synchronizers are implemented on a programmable logic device and are… 
2001
2001
An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications
A 4 Gb/s serial link tracking clock and data recovery (CDR) circuit fabricated in 0.24 /spl mu/m CMOS technology dissipates 84 mW… 
Highly Cited
1999
Highly Cited
1999
Optical signal quality monitor using direct Q-factor measurement
In photonic networks, different types of signal formats such as synchronous digital hierarchy, plesiochronous digital hierarchy… 
1997
1997
A semi-digital DLL with unlimited phase shift capability and 0.08-400 MHz operating range
The DLL consists of two loops. The core loop is a first order DLL generating six edges evenly spaced by 30/spl deg/. The… 
Highly Cited
1994
Highly Cited
1994
The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers
The Reliable Router (RR) is a network switching element targeted to two-dimensional mesh interconnection network topologies. It… 
1980
1980
Network Synchronization of Random Signals
This paper presents a unified mathematical model for studying the behavior of various network synchronization techniques, e.g… 
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