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Pipelining (DSP implementation)
Pipelining is an important technique used in several applications such as digital signal processing (DSP) systems, microprocessors, etc. It…
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Broader (1)
Digital signal processing
Microprocessor
Parallel processing (DSP implementation)
Unfolding (DSP implementation)
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
A Memristor-CMOS Braun Multiplier Array for Arithmetic Pipelining
Seungbum Baek
,
J. Eshraghian
,
Sang-Hyun Ahn
,
A. P. James
,
Kyoungrok Cho
International Conference on Electronics, Circuits…
2019
Corpus ID: 210931810
A multiplier is a core building block in most digital signal and image processing systems and increasingly so in neural…
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2018
2018
High Throughput LMS Adaptive Filter Architectures using Pipelining and Parallel Processing
A. Anirudh
,
P. Pramod
2018
Corpus ID: 196178491
Abstract In this paper, a study on existing designs of adaptive filter based on LMS algorithm is done. The primary aim is to…
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2017
2017
Offset Pipelining for Coarse Grain Reconfigurable Arrays
Aaron Wood
2017
Corpus ID: 116622215
This dissertation presents an execution model and compilation algorithms to advance the utility of coarse-grained reconfigurable…
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2014
2014
Design and Verification of Truncation-Error-Tolerant 8 Bit Signed-Multiplier
Shruti Verma
,
R.K. Jain
2014
Corpus ID: 53133417
Multiplier is one of the essential element for microprocessors, digital signal processors etc. In this project, we had proposed…
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2013
2013
Design and Simulation of Floating Point Pipelined ALU Using HDL and IP Core Generator
I. Mahi
,
S. S. Kerur
2013
Corpus ID: 212598001
Short for Arithmetic Logic Unit, ALU is one of the important components within a computer processor. It performs arithmetic…
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2013
2013
HIGH SPEED MULTIPLIER WITH PIPELINING
P. Stalin
,
K. Ranjithkumar
,
+4 authors
S. Sastha
2013
Corpus ID: 59478572
The multiplication of two higher order bits generates large number of partial products. Addition of partial products using adders…
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2010
2010
The IEEE Standards Committee P1788 for Interval Arithmetic Requires an Exact Dot Product
U. Kulisch
International Conference on Enterprise…
2010
Corpus ID: 41512829
Computing with guarantees is based on two arithmetical features. One is fixed (double) precision interval arithmetic. The other…
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2009
2009
FPGA Based Implementation of High Performance Architectural Level Low Power 32-bit RISC Core
Neenu Joseph
,
S. Sabarinath
,
K. Sankarapandiammal
International Conference on Advances in Recent…
2009
Corpus ID: 18216360
Power has become an important aspect in the design of general purpose processors. The conventional RISC processors consume too…
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2007
2007
SOPC based Asynchronous Pipelined DCT with self test capability
T. Prabakar
,
G. Lakshminarayanan
,
K. Anilkumar
Internatonal Conference on Microelectronics
2007
Corpus ID: 42812851
Asynchronous pipelined circuits have many potential advantages over their synchronous equivalents including lower power…
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2006
2006
On Improving a Pipelined Scheduling Logic
R. Gran
,
E. Morancho
,
À. Olivé
,
J. M. Llabería
2006
Corpus ID: 28354005
Pipelining the scheduling logic, which exposes and exploits the instruction level parallelism, degrades processor performance…
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