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Pipelining (DSP implementation)
Pipelining is an important technique used in several applications such as digital signal processing (DSP) systems, microprocessors, etc. It…
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Broader (1)
Digital signal processing
Microprocessor
Parallel processing (DSP implementation)
Unfolding (DSP implementation)
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
High speed efficient advanced encryption standard implementation
Soufiane Oukili
,
S. Bri
International Symposium on Networks, Computers…
2017
Corpus ID: 19485704
Cryptography is the science of secure data transmission through an insecure channel. Advanced Encryption Standard (AES) is the…
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2012
2012
Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer
A. Banerjee
,
A. Dhar
Journal of Signal Processing Systems
2012
Corpus ID: 26846423
In this paper, a pipelined architecture using CORDIC for realization of transform domain equalizer is presented. Transform domain…
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2011
2011
A pipelined 3-level bandpass delta-sigma modulator for class-S power amplifiers
Martin Schmidt
,
S. Haug
,
M. Grozing
,
M. Berroth
International Symposium on Circuits and Systems
2011
Corpus ID: 7883269
A digital bandpass delta-sigma modulator for class-S power amplifiers is presented. In comparison to a 2-level modulator coding…
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2011
2011
Design of Hardware Pipelining Processor
Pan Xue-zeng
2011
Corpus ID: 63387375
This paper proposes a hardware pipelining processor for single-threads with granularity of code block.It makes use of compile…
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2008
2008
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic
Chua-Chin Wang
,
Chi-Chun Huang
,
Ching-Li Lee
,
Tsai-Wen Cheng
IEEE Transactions on Very Large Scale Integration…
2008
Corpus ID: 6780250
A high speed and low power 8-bit carry-lookahead adder using two-phase modified dual-threshold voltage (dual-Vt) domino logic…
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2005
2005
Reducing Energy in FPGA Multipliers Through Glitch Reduction
N. Rollins
,
M. Wirthlin
2005
Corpus ID: 14144354
While FPGAs provide flexibility for performing highperformance DSP functions, they consume a significant amount of power. For…
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2005
2005
A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining
Shih-Hao Wang
,
Wen-Hsiao Peng
,
+5 authors
Tihao Chiang
J. VLSI Signal Process.
2005
Corpus ID: 18914360
We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and…
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1998
1998
A Buffering Policy for Distributed Continuous Media Servers
C. Shahabi
,
M. Alshayeji
,
Shimeng Wang
1998
Corpus ID: 17907163
Recent technological advances in computer, high-speed network, and data compression are accelerating the realization of media-on…
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Review
1994
Review
1994
Synchronous performance and reliability improvement in pipelined ASICs
Tolga Soyata
,
E. Friedman
Proceedings Seventh Annual IEEE International…
1994
Corpus ID: 16722974
The clock frequency of a synchronous circuit can be increased at the expense of increased system latency, area, and power using…
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Review
1984
Review
1984
Experience with pipelined multiple instruction streams
H. Jordan
Proceedings of the IEEE
1984
Corpus ID: 20395721
Pipelining has been used to implement efficient, high-speed vector computers. It is also an effective method for implementing…
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