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Pipelining (DSP implementation)

Pipelining is an important technique used in several applications such as digital signal processing (DSP) systems, microprocessors, etc. It… 
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Broader (1)

Digital signal processing
MicroprocessorParallel processing (DSP implementation)Unfolding (DSP implementation)

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
A Memristor-CMOS Braun Multiplier Array for Arithmetic Pipelining
A multiplier is a core building block in most digital signal and image processing systems and increasingly so in neural… 
2017
2017
Offset Pipelining for Coarse Grain Reconfigurable Arrays
This dissertation presents an execution model and compilation algorithms to advance the utility of coarse-grained reconfigurable… 
2014
2014
High Speed Advanced Encryption Standard Using Pipelining
In this paper we have proposed high throughput by swapping the AES algorithm internal stages in this proposed work shift row is… 
2013
2013
Design and Simulation of Floating Point Pipelined ALU Using HDL and IP Core Generator
Short for Arithmetic Logic Unit, ALU is one of the important components within a computer processor. It performs arithmetic… 
2012
2012
Design and Analysis of 2-Stage Pipelining High-Performance SRAM
This paper describes a SRAM design using the pipelining technique which has been used in many microprocessors extensively. The… 
2012
2012
Designand Analysis of Digital Wave Generator using CORDIC Algorithm with Pipelining and Angle Recoding Technique
CORDIC algorithm is used for calculation of complex functions in signal processing and wireless communication applications.These… 
Review
2011
Review
2011
Architectural Retiming : An Overview
Pipelining and retiming are two related techniques for improving the performance of synchronous circuits by reducing the clock… 
2009
2009
FPGA Based Implementation of High Performance Architectural Level Low Power 32-bit RISC Core
Power has become an important aspect in the design of general purpose processors. The conventional RISC processors consume too… 
2007
2007
SOPC based Asynchronous Pipelined DCT with self test capability
Asynchronous pipelined circuits have many potential advantages over their synchronous equivalents including lower power… 
2006
2006
On Improving a Pipelined Scheduling Logic
Pipelining the scheduling logic, which exposes and exploits the instruction level parallelism, degrades processor performance…