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Pin compatibility
Known as:
Compatibility
, Pin-compatibility
, Pin-compatible
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In electronics, pin-compatible devices are electronic components, generally integrated circuits or expansion cards, sharing a common footprint and…
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Related topics
Related topics
27 relations
7400 series
ARM Cortex-M
CMOS
Chipset
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
ConTutto – A Novel FPGA-based Prototyping Platform Enabling Innovation in the Memory Subsystem of a Server Class Processor
Bharat Sukhwani
,
Thomas Roewer
,
+6 authors
S. Asaad
50th Annual IEEE/ACM International Symposium on…
2017
Corpus ID: 8949069
We demonstrate the use of an FPGA as a memory buffer in a POWER8® system, creating a novel prototyping platform that enables…
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2014
2014
A Versatile Readout System for Small to Medium Scale Gaseous and Silicon Detectors
D. Calvet
IEEE Transactions on Nuclear Science
2014
Corpus ID: 34695604
This paper presents the design and performance of a readout system for gaseous and silicon detectors built for the Minos nuclear…
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2014
2014
Converting a Wireless Biotelemetry System to an Implantable System Through Antenna Redesign
Md. Shahidul Islam
,
K. Esselle
,
D. Bull
,
P. Pilowsky
IEEE Transactions on Microwave Theory and…
2014
Corpus ID: 2436309
The two major challenges associated with the conversion of a wireless system operating in air to an implantable version, antenna…
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2014
2014
The Associative Memory Serial Link Processor for the Fast TracKer (FTK) at ATLAS
A. Andreani
,
A. Annovi
,
+27 authors
P. Vulliez
2014
Corpus ID: 53595799
The Fast TracKer (FTK) is an extremely powerful and very compact processing unit, essential for efficient Level 2 trigger…
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2014
2014
Uncooled digital IRFPA-family with 17μm pixel-pitch based on amorphous silicon with massively parallel Sigma-Delta-ADC readout
D. Weiler
,
F. Hochschulz
,
+6 authors
H. Vogt
Defense + Security Symposium
2014
Corpus ID: 110295455
This paper presents the results of an advanced digital IRFPA-family developed by Fraunhofer IMS. The IRFPA-family compromises the…
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2011
2011
The Single Event Immune Reconfigurable FPGA (SIRF) Program: Development of the Radiation Hardened V5QV
C. Gordon
2011
Corpus ID: 62541555
In 2005, the Air Force Research Laboratory partnered with Xilinx Inc. to create a radiation hardened version of the VirtexTM FPGA…
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2007
2007
Analyzing the Scalability of Graph Algorithms on Eldorado
K. Underwood
,
Megan Vance
,
J. Berry
,
B. Hendrickson
IEEE International Parallel and Distributed…
2007
Corpus ID: 712432
The Cray MTA-2 system provides exceptional performance on a variety of sparse graph algorithms. Unfortunately, it was an…
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Highly Cited
2002
Highly Cited
2002
Address and data scrambling: causes and impact on memory tests
A. V. Goor
,
I. Schanstra
Proceedings First IEEE International Workshop on…
2002
Corpus ID: 15774502
The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this…
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1986
1986
An experimental 5-V-only 256-kbit CMOS EEPROM with a high-performance single-polysilicon cell
J. Miyamoto
,
J. Tsujimoto
,
+4 authors
T. Iizuka
1986
Corpus ID: 62218254
A novel single-polysilicon EEPROM cell, called DIFLOX (diffused layer controlled floating-gate-type cell with thin oxide), has…
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1980
1980
A 16 kbit electrically erasable PROM using n-channel Si-gate MNOS technology
T. Hagiwara
,
Y. Yatsuda
,
R. Kondo
,
S. Minami
,
T. Aoto
,
Y. Itoh
IEEE Journal of Solid-State Circuits
1980
Corpus ID: 10825358
A 16 kbit high performance EEPROM (electrically erasable PROM) is developed using n-channel Si-gate MNOS technology. The memory…
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