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OR gate
Known as:
4071
, OR circuit
, Or
The OR gate is a digital logic gate that implements logical disjunction - it behaves according to the truth table to the right. A HIGH output (1…
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Related topics
Related topics
50 relations
4000 series
74181
AC (complexity)
AC0
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Logical operations using phenyl ring
M. Patra
,
S. Maiti
2018
Corpus ID: 118933439
2013
2013
Transfer of Co-1 Gene Locus for Anthracnose Disease Resistance to Fresh Bean (Phaseolus vulgaris L.) Through Hybridization and Molecular Marker-Assisted Selection (MAS)
S. Y. Madakbaş
,
Mahmut Can Hiz
,
Serli Küçükyan
,
M. Sayar
2013
Corpus ID: 54860572
Anthracnose disease, caused by the fungal pathogen Colletotricum lindemuthianum brings about great yield losses in the Blacksea…
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2013
2013
A new methodology for single event transient suppression in flash FPGAs
F. Smith
Microprocessors and microsystems
2013
Corpus ID: 38170405
Review
2013
Review
2013
Models of oxygen vacancy defects involved in degradation of gate dielectrics
A. Shluger
,
K. McKenna
IEEE International Reliability Physics Symposium
2013
Corpus ID: 24918446
Capture and emission of carriers by point defects in gate dielectrics, such as SiO2 and HfO2, and at their interfaces with the…
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2009
2009
J. Blażewicz, K. Ecker, E. Pesch, G. Schmidt, J. Węglarz: Handbook on scheduling: from theory to applications
E. Levner
Journal of Scheduling
2009
Corpus ID: 35269341
2007
2007
Incorporating organizational factors into probabilistic safety assessment of nuclear power plants through canonical probabilistic models
S. F. Galán
,
A. Mosleh
,
J. Izquierdo
Reliability Engineering & System Safety
2007
Corpus ID: 14204733
2005
2005
An empirical study of the value-relevance of using proportionate consolidation accounting for investments in joint ventures
Ronald L. Stoltzfus
,
Ruth W. Epps
2005
Corpus ID: 154120544
2002
2002
Effects of high electric field and elevated-temperature bias stressing on radiation response in power VDMOSFETs
N. Stojadinovic
,
I. Manic
,
S. Djorić-Veljković
,
V. Davidović
,
S. Golubovic
,
S. Dimitrijev
Microelectronics and reliability
2002
Corpus ID: 26638807
1988
1988
Built-In Checking of the Correct Self-Test Signature
W. McAnney
,
J. Savir
IEEE Trans. Computers
1988
Corpus ID: 5582615
Description d'une procedure de determination de la valeur initiale d'un registre signature a entree simple ou multiple
1973
1973
Combinational and Sequential Cellular Structures
S. Kukreja
,
I. Chen
IEEE transactions on computers
1973
Corpus ID: 30660127
Cellular arrays composed of identical cells with uniform interconnections are presented. The basic cell is a switching device…
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