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NAND gate
Known as:
Negated AND gate
, NAND circuit
, No AND gate
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In digital electronics, a NAND gate (negative-AND) is a logic gate which produces an output which is false only if all its inputs are true; thus its…
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Related topics
Related topics
34 relations
4000 series
7400 series
AND gate
Boolean algebra
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Quantum Dynamic Programming Algorithm for DAGs. Applications for AND-OR DAG Evaluation and DAG's Diameter Search
K. Khadiev
arXiv.org
2018
Corpus ID: 13746887
In this paper, we present Quantum Dynamic Programming approach for problems on directed acycling graphs (DAGs). The algorithm has…
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2018
2018
Optical interactions for internal signal tracking in ICs
I. Vogt
2018
Corpus ID: 188334063
This work investigates and improves two common techniques of electronics failure analysis, (spectral) photon emission microscopy…
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2014
2014
Flexible NAND-Like Organic Ferroelectric Memory Array
Benjamin Kam
,
T. Ke
,
+9 authors
P. Heremans
IEEE Electron Device Letters
2014
Corpus ID: 23100690
We present a memory array of organic ferroelectric field-effect transistors (OFeFETs) on flexible substrates. The OFeFETs are…
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2006
2006
Fault-pattern oriented defect diagnosis for flash memory
Mu-Hsien Hsu
,
Yu-Tsao Hsing
,
J. Yeh
,
Cheng-Wen Wu
Memory Technology, Design, and Testing
2006
Corpus ID: 6472328
In order to ease the time-to-market pressure of flash memory, we propose a fault-pattern based diagnosis methodology that reduces…
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1993
1993
A Biochemical “NAND” Gate and Assorted Circuits
H. Sauro
1993
Corpus ID: 60065029
The study of metabolic cascades is often associated with the notion of ‘switches’, that is, mechanisms that can exist in one of…
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1992
1992
A Study of High-Performance NAND Structured EEPROMS
T. Endoh
,
R. Shirota
,
S. Aritome
,
F. Masuoka
1992
Corpus ID: 113470573
1980
1980
A 64Kb static RAM
T. Ohzone
,
Shuji Kondo
,
K. Tsuji
,
Tsuyoshi Shiragasawa
,
Takeshi lshihara
,
S. Horiuchi
IEEE International Solid-State Circuits…
1980
Corpus ID: 37016341
THIS PAPER WILL REPORT on the application of double-level polysilicon’ and NMOS/CMOS process technologies to the design of a 64Kb…
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Review
1977
Review
1977
Review of Digital system implementation by Gerrit A. Blaauw. Prentice Hall, Series in Automatic Computatin 1976.
G. Chroust
CARN
1977
Corpus ID: 31254481
In order to define the architecture of the adder (chapter 2) a diagram is given which is immediately translated into a APL…
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1972
1972
A simple charge regenerator for use with charge-transfer devices and the design of functional logic arrays
M. Tompsett
1972
Corpus ID: 62308102
An inverting binary-charge regenerator for use with new charge- transfer devices (charge-coupled and integrated MOS bucket…
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1966
1966
The Universal Logic Block (ULB) and its Application to Logic Design
D. C. Forslund
,
R. Waxman
Scandinavian Workshop on Algorithm Theory
1966
Corpus ID: 28949839
This report describes the techniques used to obtain two three-variable universal logic blocks from NAND circuits. The emphasis…
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