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Memory ordering
Memory ordering describes the order of accesses to computer memory by a CPU. The term can refer either to the memory ordering generated by the…
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Related topics
Related topics
25 relations
CPU cache
Compile time
Compiler
Dekker's algorithm
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Broader (3)
Computer architecture
Computer memory
Concurrency (computer science)
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Weak Memory Models as LLVM-to-LLVM Transformations
V. Still
,
Petr Ročkai
,
J. Barnat
Doctoral Workshop on Mathematical and Engineering…
2015
Corpus ID: 42696137
Data races are among the most difficult software bugs to discover. They arise from multiple threads accessing the same memory…
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2009
2009
A Storage Algorithm for a Kanerva-like Memory Model
S. Ribaric
,
Darijan Marcetic
2009
Corpus ID: 192667881
2009
2009
Merced Proceedings of the Annual Meeting of the Cognitive Science Society Title The Inverse List Length Effect : Implications for Exemplar Models of Recognition Memory
Permalink
2009
Corpus ID: 73624244
A. H. Criss and R. M. Shiffrin (2004) argued against the composite context noise explanation of recognition memory introduced by…
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2008
2008
Memory model effects on application performance for a lightweight multithreaded architecture
Sheng Li
,
Shannon K. Kuntz
,
P. Kogge
,
J. Brockman
IEEE International Symposium on Parallel and…
2008
Corpus ID: 9927640
In this paper, we evaluate the effects of a partitioned global address space (PGAS) versus aflat, randomized distributed global…
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2007
2007
Memory Ordering in Modern Microprocessors
P. McKenney
2007
Corpus ID: 40907
Summary of Memory Ordering When it comes to how memory ordering works on dif-ferent CPUs, there is good news and bad news.The bad…
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2006
2006
Conditional Memory Ordering
C. V. Praun
,
Harold W. Cain
,
Jong-Deok Choi
,
K. D. Ryu
International Symposium on Computer Architecture
2006
Corpus ID: 8901083
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own…
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2006
2006
Multiprocessor Memory Model Verification
P. Loewenstein
,
Shailender Chaudhry
,
R. Cypher
,
Chaiyasit Manovit
2006
Corpus ID: 16763816
Summary. Using the system architects’ specified memory ordering as a function of execution, a multiprocessing system can be veri…
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2005
2005
Memory ordering in modern microprocessors, Part I
P. McKenney
2005
Corpus ID: 53763281
A medical timer apparatus being suitable for use with both integral and non-integral medication containers, and having a…
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2004
2004
A High-Bandwidth Load-Store Unit for Single- and Multi-Threaded Processors
A. Roth
2004
Corpus ID: 2855289
A store queue (SQ) is a critical component of the load execution machinery. High ILP processors require high load execution…
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1985
1985
A Memory Model : Neural Network Storing and Recalling Information in the Form of Bursts of Nerve Impulses
K. Tsutsumi
,
H. Matsumoto
1985
Corpus ID: 63400180
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