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Intel Core (microarchitecture)
Known as:
Intel Core microarchitecture
, Intel Core 2 Solo ULV
, Intel Core Architecture
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The Intel Core microarchitecture (previously known as the Next-Generation Micro-Architecture) is a multi-core processor microarchitecture unveiled by…
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Related topics
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50 relations
BIOS
CPU cache
CPU power dissipation
CPUID
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2013
Highly Cited
2013
Automatic Performance Tuning (Autotuning)
James Demmel
,
Sam Williams
,
+9 authors
Andrew Waterman
2013
Corpus ID: 7289478
Understanding the most efficient design and utilization of emerging multicore systems is one of the most challenging questions…
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Highly Cited
2012
Highly Cited
2012
3D-MAPS: 3D Massively parallel processor with stacked memory
Daehyun Kim
,
K. Athikulwongse
,
+20 authors
S. Lim
IEEE International Solid-State Circuits…
2012
Corpus ID: 5010492
Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration, but none of them involves…
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Highly Cited
2010
Highly Cited
2010
Layered label propagation: a multiresolution coordinate-free ordering for compressing social networks
P. Boldi
,
M. Rosa
,
Massimo Santini
,
S. Vigna
The Web Conference
2010
Corpus ID: 1689835
We continue the line of research on graph compression started with WebGraph, but we move our focus to the compression of social…
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Highly Cited
2009
Highly Cited
2009
Implementing sparse matrix-vector multiplication on throughput-oriented processors
Nathan Bell
,
M. Garland
Proceedings of the Conference on High Performance…
2009
Corpus ID: 14531936
Sparse matrix-vector multiplication (SpMV) is of singular importance in sparse linear algebra. In contrast to the uniform…
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Highly Cited
2008
Highly Cited
2008
Efficient Sparse Matrix-Vector Multiplication on CUDA
Nathan Bell
,
M. Garland
2008
Corpus ID: 11725419
,
Highly Cited
2008
Highly Cited
2008
Corona: System Implications of Emerging Nanophotonic Technology
D. Vantrease
,
R. Schreiber
,
+7 authors
Jung Ho Ahn
International Symposium on Computer Architecture
2008
Corpus ID: 6002052
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the…
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Review
2007
Review
2007
The Application of Hidden Markov Models in Speech Recognition
M. Gales
,
S. Young
Foundations and Trends® in Signal Processing
2007
Corpus ID: 51039442
Hidden Markov Models (HMMs) provide a simple and effective framework for modelling time-varying spectral vector sequences. As a…
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Highly Cited
2007
Highly Cited
2007
Thousand Core ChipsA Technology Perspective
S. Borkar
44th ACM/IEEE Design Automation Conference
2007
Corpus ID: 6091957
This paper presents the many-core architecture, with hundreds to thousands of small cores, to deliver unprecedented compute…
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Highly Cited
2006
Highly Cited
2006
Inside Intel® Core microarchitecture
Jack Doweck
IEEE Hot Chips Symposium
2006
Corpus ID: 45795969
This article consists of a collection of slides from the author's conference presentation on Intel's Core product line's…
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Highly Cited
2006
Highly Cited
2006
Fast and memory-efficient regular expression matching for deep packet inspection
Fang Yu
,
Z. Chen
,
Y. Diao
,
T. V. Lakshman
,
R. Katz
Symposium on Architecture For Networking And…
2006
Corpus ID: 3449616
Packet content scanning at high speed has become extremely important due to its applications in network security, network…
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