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An instruction window in computer architecture refers to the set of instructions which can execute out of order in an out-of-order speculative CPU…
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Related topics
Related topics
5 relations
Computer architecture
Out-of-order execution
Re-order buffer
Shelving buffer
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Exploiting criticality to reduce bottlenecks in distributed uniprocessors
Behnam Robatmili
,
Madhu Saravana Sibi Govindan
,
D. Burger
,
S. Keckler
IEEE 17th International Symposium on High…
2011
Corpus ID: 6537785
Composable multicore systems merge multiple independent cores for running sequential single-threaded workloads. The performance…
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2006
2006
Novel low-overhead operand isolation techniques for low-power datapath synthesis
N. Banerjee
,
A. Raychowdhury
,
K. Roy
,
S. Bhunia
,
H. Mahmoodi
ICCD
2006
Corpus ID: 7843646
Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications…
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2006
2006
Critical path analysis of the TRIPS architecture
Ramadass Nagarajan
,
Xia Chen
,
Robert G. McDonald
,
D. Burger
,
S. Keckler
IEEE International Symposium on Performance…
2006
Corpus ID: 1870930
Fast, accurate, and effective performance analysis is essential for the design of modern processor architectures and improving…
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2005
2005
Exploiting Load/Store Parallelism via Memory Dependence Prediction
Andreas Moshovos
2005
Corpus ID: 64439253
Since memory reads or loads are very frequent, memory latency, that is the time it takes for memory to respond to requests can…
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2004
2004
Defining wakeup width for efficient dynamic scheduling
Aneesh Aggarwal
,
M. Franklin
,
Oğuz Ergin
IEEE International Conference on Computer Design…
2004
Corpus ID: 607963
A larger dynamic scheduler (DS) exposes more instruction level parallelism (ILP), giving better performance. However, a larger DS…
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2003
2003
Modeling And Performance Evaluation Of Branch And Value Prediction In Ilp Processors
M. Gusev
,
P. Mitrevski
International Journal of Computational…
2003
Corpus ID: 18312978
Speculative execution is one of the key issues to boost the performance of future generation microprocessors. In this paper, we…
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2001
2001
A 1.8 GHz Instruction Window Buffer
J. Leenstra
,
J. Pille
,
A. Müler
,
W. Sauer
,
Rolf Sautter
,
D. Wendel
IEEE International Solid-State Circuits…
2001
Corpus ID: 24871581
An Instruction Window Buffer (IWB) addresses the challenges in microprocessor designs beyond a GHz. The IWB implements the…
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1999
1999
The design space of shelving
D. Sima
Journal of systems architecture
1999
Corpus ID: 17815170
1995
1995
Precise exception handling for a self-timed processor
W. Richardson
,
E. Brunvand
Proceedings of ICCD '95 International Conference…
1995
Corpus ID: 6799222
Self-timed systems structured as multiple concurrent processes and communicating through self-timed queues are a convenient way…
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Highly Cited
1989
Highly Cited
1989
Super-scalar processor design
William M. Johnson
1989
Corpus ID: 18921209
A super-scalar processor is one that is capable of sustaining an instruction-execution rate of more than one instruction per…
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