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Instruction window
An instruction window in computer architecture refers to the set of instructions which can execute out of order in an out-of-order speculative CPU…
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Related topics
Related topics
5 relations
Computer architecture
Out-of-order execution
Re-order buffer
Shelving buffer
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
An Improvement of Switch-on-Future-Event Multithreading
Yota
,
Hioya
,
+5 authors
akai
2010
Corpus ID: 160422
“Delinquent” instructions are a small number of static instructions that cause most branch prediction misses and cache misses in…
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2009
2009
PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization
Wei Mi
,
Xiaobing Feng
,
Yao-Cang Jia
,
Li Chen
,
Jingling Xue
Journal of Computational Science and Technology
2009
Corpus ID: 25077023
DRAM row buffer conflicts can increase memory access latency significantly. This paper presents a new page-allocation-based…
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2009
2009
Memory Consistency Verification Under Time Order Restriction
Yunji Chen
,
Yi Lv
,
+4 authors
Hong Pan
2009
Corpus ID: 73603978
The verification of an execution against memory consistency is known to be NP-hard. This paper proposes a novel fast memory…
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Review
2007
Review
2007
Scaling Instruction Window
Shiliang Liu
2007
Corpus ID: 2488479
Contemporary superscalar processors employ large instruction window to tolerate long latency (mainly second-level cache misses…
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2006
2006
Instruction-Window Power Reduction Using Data Dependence Metric
Z. Youssfi
,
M. Shanblatt
2006
Corpus ID: 9720186
A large portion of the power consumed by a highperformance out-of-order microprocessor is attributed to units within the…
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2005
2005
Exploiting Load/Store Parallelism via Memory Dependence Prediction
Andreas Moshovos
2005
Corpus ID: 64439253
Since memory reads or loads are very frequent, memory latency, that is the time it takes for memory to respond to requests can…
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2001
2001
Performance Analysis of Superscalar Processors Using A Queueing Model
Y. Zhu
,
W. Wong
2001
Corpus ID: 18631645
Performance Analysis of Sup erscalar Pro cessors Using AQueueing Mo delY. Zhu and W.F. WongDepartment of Information Systems and…
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2001
2001
Speculative multi-threading lets us fashion a large instruction window
L. Barroso
,
K. Gharachorloo
,
+7 authors
R. Stets
2001
Corpus ID: 1008305
Computer parently reordering instructions from nearby program regions, but even sophisticated compiler scheduling is…
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2000
2000
The Curriculum and the Interface: A Componential Analysis of the Learning Curve
K. Gluck
,
Marsha C. Lovett
,
John R. Anderson
,
V. Shute
2000
Corpus ID: 17875465
This paper presents a quantitative assessment of the importance of adaptation to the learning environment as a component of the…
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1994
1994
Instruction Window Characterization of
P. Dubey
,
G. Adams
1994
Corpus ID: 61742405
Detecting independent operations is a prime objec- tive for computers that are capable of issuing and executing multiple…
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