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High-speed transceiver logic
Known as:
Hstl
High-speed transceiver logic or HSTL is a technology-independent standard for signaling between integrated circuits. The nominal signaling range is 0…
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Related topics
Related topics
4 relations
Broader (1)
Digital electronics
Integrated circuit
Media-independent interface
Stub Series Terminated Logic
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
HSTL and HSUL I/O Standard Based Energy-Efficient Control Unit Circuit Design on FPGA
Keshav Kumar
,
Pushpanjali Pandey
Gyancity Journal of Electronics and Computer…
2019
Corpus ID: 209079515
2018
2018
Design of Energy-Efficient Random Access Memory Circuit Using Low-Voltage CMOS and High-Speed Transreceiver Logic-I I/O Standard on 28 nm FPGA
Tarun Agrawal
,
V. Srivastava
2018
Corpus ID: 67193088
In this paper, we are designing an efficient memory using LVCMOS and HSTL-I IO Standards on 28 nm (Artix-7) FPGA. There are…
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2017
2017
Aalborg Universitet FPGA Based Efficient Design of Traffic Light Controller using Frequency Scaling for Family of
Shivani Sharma
,
S. Khan
,
B. Das
,
N. Pandey
,
M. D.
,
Akbar Hussain
2017
Corpus ID: 56099909
Traffic blockage is one of the major issues faced by world today. That can be road traffic or air traffic or even water traffic…
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2017
2017
Smart Communication Network design with application of Energy Efficient Digital Clock for Monitoring of Time -To-Live (TTL)
T. Singhal
,
Abhishek Shrivastava
,
Palash Jain
,
Rahul
,
Gaurav D. Verma
2017
Corpus ID: 63451719
We are using term smart in two contexts, one context it is able to monitor Time to Live (TTL) with integration of digital clock…
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2016
2016
Aalborg Universitet Power Analysis of Energy Efficient DES Algorithm and Implementation on 28 nm FPGA
Vandana Thind
,
Dil Muhammad Akbar Bishwajeet Hussain
2016
Corpus ID: 66269196
in this work, we have done power analysis of Data Encryption Standard (DES) algorithm using Xilinx ISE software development kit…
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2016
2016
HSTL IO Standards Based Processor Specific Green Counter Design on 90nm FPGAAbhay Saxena
Abhay Saxena
,
Ashutosh Bhatt
,
B. Pandey
,
Praveen Tripathi
,
G. Dutt
2016
Corpus ID: 63988387
Extending battery life and increase in portability of modern electronic devices and gadgets are the main motives behind the Green…
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2015
2015
HSTL Based Energy Efficient Vedic Multiplier Design on 28 nm FPGA Using Vedic Formula Adyamadyenantya
Arushi Aggarwal
2015
Corpus ID: 64327055
In this paper we have designed energy efficient Vedic multiplier circuit with units of inch or sq. ft. using family of various…
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2014
2014
Challenges and new prospects in hepatosplenic g d T-cell lymphoma
Marco Calvaruso
,
A. Gulino
,
+6 authors
A. Florena
2014
Corpus ID: 37795907
1 Laboratorio di Tecnologie Oncologiche – HSR Giglio, C. da Pietrapollastra-Pisciotto, Cefal ù , Italy, 2 Dipartimento di Scienze…
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Review
2011
Review
2011
Data Transmission Specific Simulation of Transmission Line using HSTL
Sokehwan Kim
,
C. Hur
2011
Corpus ID: 58712133
Tosin backplane system design of this study (Backplane) from the HSTL (High-Speed Transceiver Logic) characteristics of the…
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2005
2005
Design andVerification ofCMOS HSTL Buffers YF HSTLO18
Shaoquan Gao
2005
Corpus ID: 209750392
HSTLlevel standard isnewtechnology for high-speed data transmission. Basedontheanalysis of applications, a coupleof I/Obuffers…
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