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High-speed transceiver logic
Known as:
Hstl
High-speed transceiver logic or HSTL is a technology-independent standard for signaling between integrated circuits. The nominal signaling range is 0…
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Related topics
Related topics
4 relations
Broader (1)
Digital electronics
Integrated circuit
Media-independent interface
Stub Series Terminated Logic
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
HSTL and HSUL I/O Standard Based Energy-Efficient Control Unit Circuit Design on FPGA
K. Kumar
,
Pushpanjali Pandey
Gyancity Journal of Electronics and Computer…
2019
Corpus ID: 209079515
2018
2018
Design of Energy-Efficient Random Access Memory Circuit Using Low-Voltage CMOS and High-Speed Transreceiver Logic-I I/O Standard on 28 nm FPGA
Tarun Agrawal
,
V. Srivastava
2018
Corpus ID: 67193088
In this paper, we are designing an efficient memory using LVCMOS and HSTL-I IO Standards on 28 nm (Artix-7) FPGA. There are…
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2017
2017
Aalborg Universitet FPGA Based Efficient Design of Traffic Light Controller using Frequency Scaling for Family of
Shivani Sharma
,
S. Khan
,
B. Das
,
N. Pandey
,
M. D
,
Akbar Hussain
2017
Corpus ID: 56099909
Traffic blockage is one of the major issues faced by world today. That can be road traffic or air traffic or even water traffic…
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2015
2015
FPGA Based Low Power Router Design Using High Speed Transeceiver Logic IO Standard
Vandana Thind
,
D. A. Hussain
2015
Corpus ID: 54903698
Communication is the major aspect that plays an important role in success of any organization. Information in the same way is…
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2015
2015
IO Standard based low power memory design and implementation on FPGA
Ravinder Kaur
,
J. Kumar
,
Sumita Nagah
,
B. Pandey
,
Kavita Goswami
International Conference on Computing for…
2015
Corpus ID: 14175058
In this work of low power memory design on FPGA, we are using the most energy efficient I/O standard among LVCMOS, HSLVDCI, HSTL…
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2014
2014
Design of power optimized memory circuit using High Speed Transreceiver Logic IO Standard on 28nm Field Programmable Gate Array
Sweety
,
B. Pandey
,
T. Kumar
,
T. Das
International Conference on Reliability…
2014
Corpus ID: 10880469
In this work, we designed a power efficient memory circuit using family of various HSTL IO Standards on 28nm Field Programmable…
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2014
2014
Challenges and new prospects in hepatosplenic g d T-cell lymphoma
Marco Calvaruso
,
A. Gulino
,
+6 authors
A. Florena
2014
Corpus ID: 37795907
1 Laboratorio di Tecnologie Oncologiche – HSR Giglio, C. da Pietrapollastra-Pisciotto, Cefal ù , Italy, 2 Dipartimento di Scienze…
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2014
2014
Simulation of energy efficient Bi-directional Visitor Counting Machine on FPGA
S. Islam
,
Md. Mahbub-E-Noor
,
+4 authors
B. Pandey
International Conference on Reliability…
2014
Corpus ID: 34565097
In this paper we are presenting result of simulation based energy efficient bi-directional visitor counting machine (VCM) on FPGA…
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2014
2014
Simulation of HSTL IO standard based energy efficient Punjabi Unicode reader on FPGA
B. Pandey
,
Gurpreet Singh
,
Rashid Siddique Parhyar
,
Umar Farooq
,
T. Kumar
International Conference on Open Source Systems…
2014
Corpus ID: 35414151
Punjabi is ranked 1st in languages of Pakistan [5], 11th in Indian languages [6] and 3rd in Indian Subcontinent. In order to…
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2005
2005
Design and verification of CMOS HSTL buffers - YF/spl I.bar/HSTL018
Shaoquan Gao
,
Jihua Chen
,
Jianwu Ma
,
Ting Liu
International Conference on ASIC
2005
Corpus ID: 13456828
HSTL level standard is technology for high-speed data transmission. Based on the analysis of applications, a couple of I/O…
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