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Harvard architecture

Known as: Harvard (disambiguation) 
The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term… 
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4-bitARM architectureATHENA computerAthlon

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
A Technique Preventing Code Reuse Attacks Based on RISC Processor
A full-process tag inspection system was designed and experimentally verified. This system based on RISC processors can defend… 
2017
2017
OpenRRArch: una arquitectura abierta, robusta y confiable para el control de robots autónomos
Contexto: Los sistemas de control y navegacion de robots autonomos constituyen un dinamico campo de investigacion en robotica… 
2013
2013
Hardware requirements of communication-centric machine learning algorithms
Machine learning type neuromorphic algorithms have the potential to enable the brains behind small autonomous robots, provided… 
2010
2010
Minimal Instruction Set AES Processor using Harvard Architecture
This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC… 
2009
2009
List of Criteria for a Secure Computer Architecture
The security of a digital system depends directly onthe security of the hardware platform the system is based on.The analysis of… 
Review
2007
Review
2007
Chapter 2 – Overview of the Cortex-M3
2005
2005
Structure of the PSoC
2001
2001
OPTIMIZING DIGITAL MUSICAL EFFECT IMPLEMENTATION FOR HARVARD DSP ARCHITECTURE
Alternator circuit arrangement (20) for controlling the electrical energization of multiple load devices such as two pump motors… 
1993
1993
Translating Signal Flowcharts into Microcode for Custom Digital Signal Processors
The retargetable microcode compiler CBC suited for application specific DSP (ASDSP) system software development is presented. The… 
1992
1992
Evaluation of a 'stall' cache: an efficient restricted onchip instruction cache
The paper compares the cost and performance of a new kind of restricted instruction cache architecture-the stall cache-against… 
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