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Harvard architecture
Known as:
Harvard (disambiguation)
The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term…
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Related topics
Related topics
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4-bit
ARM architecture
ATHENA computer
Athlon
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
A Technique Preventing Code Reuse Attacks Based on RISC Processor
Yang Li
,
Jun-Wei Li
DEStech Transactions on Computer Science and…
2018
Corpus ID: 69484729
A full-process tag inspection system was designed and experimentally verified. This system based on RISC processors can defend…
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2018
2018
Implementation of the Sound Classification Module on the Platform with Limited Resources
Nives Kaprocki
,
Nenad Pekez
,
J. Kovacevic
Zooming Innovation in Consumer Technologies…
2018
Corpus ID: 52152459
There is a growing trend of using algorithms based on deep and machine learning in consumer devices, which imposes a challenge to…
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2017
2017
OpenRRArch: una arquitectura abierta, robusta y confiable para el control de robots autónomos
Fredy Hernán Martínez Sarmiento
,
D. A. Ramírez
2017
Corpus ID: 116285866
Contexto: Los sistemas de control y navegacion de robots autonomos constituyen un dinamico campo de investigacion en robotica…
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2015
2015
Chapter 3 – Microprocessor Primer
Xiaocong Fan
2015
Corpus ID: 59763352
2013
2013
Hardware requirements of communication-centric machine learning algorithms
L. Koskinen
,
Enrico Roverato
NASA/ESA Conference on Adaptive Hardware and…
2013
Corpus ID: 9014272
Machine learning type neuromorphic algorithms have the potential to enable the brains behind small autonomous robots, provided…
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2011
2011
A median filter FPGA with Harvard Architecture
Zhao Junxia
,
Zhen Botao
,
L. HongJun
International Conference on Information and…
2011
Corpus ID: 1532810
To improve the speed of the image processing chip, to quick share the market and to reduce costs, this paper designs a chip with…
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Review
2007
Review
2007
Chapter 2 – Overview of the Cortex-M3
Joseph Yiu
2007
Corpus ID: 67060485
2005
2005
Structure of the PSoC
R. Ashby
2005
Corpus ID: 56667175
1993
1993
Translating Signal Flowcharts into Microcode for Custom Digital Signal Processors
A. Fauth
,
A. Knoll
1993
Corpus ID: 15340822
The retargetable microcode compiler CBC suited for application specific DSP (ASDSP) system software development is presented. The…
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1992
1992
Evaluation of a 'stall' cache: an efficient restricted onchip instruction cache
K. Schauser
,
K. Asanovi
,
David A Patterson
,
Edward H F Rank
Proceedings of the Twenty-Fifth Hawaii…
1992
Corpus ID: 17139907
The paper compares the cost and performance of a new kind of restricted instruction cache architecture-the stall cache-against…
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