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Half-precision floating-point format

Known as: Float16, Half-float, Half-precision 
In computing, half precision is a binary floating-point computer number format that occupies 16 bits (two bytes in modern computers) in computer… Expand
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2018
Highly Cited
2018
Mixed Precision Training
Deep neural networks have enabled progress in a wide variety of applications. Growing the size of the neural network typically… Expand
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Highly Cited
2018
Highly Cited
2018
Exascale Deep Learning for Climate Analytics
We extract pixel-level masks of extreme weather patterns using variants of Tiramisu and DeepLabv3+ neural networks. We describe… Expand
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Highly Cited
2018
Highly Cited
2018
Norm matters: efficient and accurate normalization schemes in deep networks
Over the past few years batch-normalization has been commonly used in deep networks, allowing faster training and high… Expand
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2017
2017
Towards numerical benchmark for half-precision floating point arithmetic
With NVIDA Tegra Jetson X1 and Pascal P100 GPUs, NVIDIA introduced hardware-based computation on FP16 numbers also called half… Expand
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Highly Cited
2017
Highly Cited
2017
SCALEDEEP: A scalable compute architecture for learning and evaluating deep networks
Deep Neural Networks (DNNs) have demonstrated state-of-the-art performance on a broad range of tasks involving natural language… Expand
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2014
2014
Lattice QCD with Domain Decomposition on Intel® Xeon Phi Co-Processors
The gap between the cost of moving data and the cost of computing continues to grow, making it ever harder to design iterative… Expand
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Highly Cited
2010
Highly Cited
2010
Solving lattice QCD systems of equations using mixed precision solvers on GPUs
Abstract Modern graphics hardware is designed for highly parallel numerical tasks and promises significant cost and performance… Expand
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2010
2010
Half-BPS solutions locally asymptotic to AdS3 × S3 and interface conformal field theories
Type IIB superstring theory has AdS3 × S3 × M4 (where the manifold M4 is either K3 or T4) solutions which preserve sixteen… Expand
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2009
2009
Design and Implementation and On-Chip High-Speed Test of SFQ Half-Precision Floating-Point Adders
We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a… Expand
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Highly Cited
2008
Highly Cited
2008
Janus configurations, Chern-Simons couplings, and The θ-Angle in $ \mathcal{N} = 4 $ super Yang-Mills theory
We generalize the half-BPS Janus configuration of four-dimensional $ \mathcal{N} = 4 $ super Yang-Mills theory to allow the theta… Expand
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