Skip to search formSkip to main contentSkip to account menu

GDDR SDRAM

Known as: GDDR 
Graphics DDR SDRAM (GDDR SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) specifically designed for graphics processing units… 
Wikipedia (opens in a new tab)

Related topics

Related topics

3 relations
Double data rateGraphics processing unitSingle instruction, multiple threads

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Heavy Ion Single Event Effects Measurements of 512Mb ISSI SDRAM
Heavy ion single-event measurements on 512Mb ISSI synchronous dynamic random-access memory (SDRAM) are reported. Heavy ion… 
2015
2015
The Gene Expression Identification and Elementary Functional Analysis of GDDR Transgenic Mice
Objective: To provide a reliable animal model for the study of deep step GDDR( Gastric Dramatic Down-related)biological functions… 
2014
2014
Evaluation of DGEMM Implementation on Intel Xeon Phi Coprocessor
In this paper we will present a detailed study of implementing double-precision matrix-matrix multiplication (DGEMM) utilizing… 
2011
2011
Realtime scheduling using GPUs - proof of feasibility
This paper will report our evaluation to use openCL as a platform for hard realtime scheduling. Specifically, we have evaluated… 
2010
2010
High-Speed Memory Interfaces -- DDR/GDDR-DRAM
2009
2009
Efficient Multiplication of Polynomials on Graphics Hardware
We present the algorithm to multiply univariate polynomials with integer coefficients efficiently using the Number Theoretic… 
2009
2009
Clock jitter modeling in statistical link simulation
  • D. OhSam Chang
  • IEEE 18th Conference on Electrical Performance of…
  • 2009
  • Corpus ID: 26631463
Statistical link analysis has gained significant importance as high-speed interconnect designs require accurate bit error rate… 
2007
2007
Dynamic Single Event Upset Characterization of the MT48LC4M32B2TG-6 SDRAM Using Proton Irradiation
Dynamic single event upset characterization of the MT48LC4M32B2TG-6 SDRAM using proton irradiation is presented. The device's… 
2005
2005
A Low Power High Performance Register-Controlled Digital DLL for 2Gbps x32 GDDR SDRAM
A new low power high performance register-controlled digital delay locked loop (LPRCDLL) is presented. The circuit has fine delay… 
2003
2003
Weird turn of events in continuing rambus saga
In the ongoing Rambus saga, the latest development now casts Rambus as the alleged victim of an antitrust conspiracy. What's more… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)