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FIFO (computing and electronics)
Known as:
Last in, last out
, FCFS (computing)
, First-in, first out
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FIFO is an acronym for first in, first out, a method for organizing and manipulating a data buffer, where the oldest (first) entry, or 'head' of the…
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Related topics
Related topics
50 relations
8250 UART
Actor model
Amortized analysis
Anonymous pipe
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Broader (1)
Inter-process communication
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2007
Highly Cited
2007
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
Christopher Claus
,
Florian Helmut Müller
,
J. Zeppenfeld
,
W. Stechele
IEEE International Parallel and Distributed…
2007
Corpus ID: 8617311
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial…
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2005
2005
On the effect of router buffer sizes on low-rate denial of service attacks
S. Sarat
,
A. Terzis
Proceedings. 14th International Conference on…
2005
Corpus ID: 15655855
Router queues buffer packets during congestion epochs. A recent result by Appenzeller et al. showed that the size of FIFO queues…
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Highly Cited
2004
Highly Cited
2004
Applying scheduling techniques to minimize the number of late jobs in workflow systems
Gregório Baggio
,
Jacques Wainer
,
C. Ellis
ACM Symposium on Applied Computing
2004
Corpus ID: 15336988
Ordering the cases in a workflow can result in significant decrease on the number of late jobs. But merging workflow and…
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Highly Cited
2001
Highly Cited
2001
Colif: A Design Representation for Application-Specific Multiprocessor SOCs
W. Cesário
,
G. Nicolescu
,
L. Gauthier
,
D. Lyonnard
,
A. Jerraya
IEEE Design & Test of Computers
2001
Corpus ID: 17942864
By separating component behavior and communication infrastructure and spanning multiple abstraction levels, Colif lets designers…
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Highly Cited
1998
Highly Cited
1998
A Quantitative Comparison of Iterative Scheduling Algorithms for Input-Queued Switches
N. McKeown
,
T. Anderson
Comput. Networks
1998
Corpus ID: 958406
Highly Cited
1996
Highly Cited
1996
Packet network simulation: speedup and accuracy versus timing granularity
Jong-Suk Ahn
,
P. Danzig
TNET
1996
Corpus ID: 28496693
This paper describes a new technique that can speedup simulation of high-speed, wide-area packet networks by one to two orders of…
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Highly Cited
1993
Highly Cited
1993
Queuing spin lock algorithms to support timing predictability
Travis S. Craig
Proceedings Real-Time Systems Symposium
1993
Corpus ID: 2059726
We introduce practical new algorithms for FIFO and priority-ordered spin locks on shared-memory multiprocessors with an atomic…
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Highly Cited
1989
Highly Cited
1989
Output-buffer switch architecture for asynchronous transfer mode
H. Suzuki
,
H. Nagano
,
T. Suzuki
,
Takeuchi Takao
,
S. Iwasaki
IEEE International Conference on Communications…
1989
Corpus ID: 60578651
An asynchronous transfer mode (ATM) switch architecture for the broadband integrated services digital network (ISDN) is proposed…
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Highly Cited
1984
Highly Cited
1984
A Tool for Structured Functional Simulation
D. Messerschmitt
IEEE Journal on Selected Areas in Communications
1984
Corpus ID: 2166478
BLOSIM is a general purpose time-driven (as opposed to event-driven) simulation language. It is written in C language, and is…
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Highly Cited
1984
Highly Cited
1984
Synthesis of Communicating Finite-State Machines with Guaranteed Progress
M. Gouda
,
Yao-Tin Yu
IEEE Transactions on Communications
1984
Corpus ID: 8666564
We present a methodology to synthesize two communicating finite-state machines which exchange messages over two one-directional…
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