Skip to search formSkip to main contentSkip to account menu

Effective number of bits

Known as: ENOB 
Effective number of bits (ENOB) is a measure of the dynamic range of an analog-to-digital converter (ADC) and its associated circuitry. The… 
Wikipedia (opens in a new tab)

Related topics

Related topics

9 relations
Analog-to-digital converterDigital-to-analog converterDistortionDynamic range

Broader (1)

Digital signal processing

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
A 0.6 V 10 bit 120 kS/s SAR ADC for implantable multichannel neural recording
A 10 bit fully-differential SAR ADC with multiple input channels is proposed for neural recording implants. The proposed SAR ADC… 
2014
2014
An 8-bit 100-GS/s distributed DAC in 28-nm CMOS
An 8-bit 100-GS/s digital-to-analog converter (DAC) using a distributed output topology in 28-nm low-power CMOS is presented. The… 
Review
2012
Review
2012
Design and Assessment of a 6 ps-Resolution Time-to-Digital Converter With 5 MGy Gamma-Dose Tolerance for LIDAR Application
Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog… 
2012
2012
1-1-1 MASH $\Delta \Sigma$ Time-to-Digital Converters With 6 ps Resolution and Third-Order Noise-Shaping
Two 1-1-1 MASH ΔΣ time-to-digital converters (TDCs) are presented in this paper. Third-order time domain noise-shaping has been… 
2009
2009
A 1 GHz Bandwidth Low-Pass $\Delta \Sigma$ ADC With 20–50 GHz Adjustable Sampling Rate
A low-pass continuous-time delta-sigma data converter with adjustable sampling rate from 20-50 GS/s has been demonstrated in a… 
2009
2009
A 6b 3GS/s flash ADC with background calibration
A 6b 3GS/s flash ADC is implemented in a 90nm CMOS process. The proposed ADC is based on an interpolating flash architecture… 
2009
2009
A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-µm digital CMOS process
This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for… 
Highly Cited
2007
Highly Cited
2007
A Low-Noise 40-GS/s Continuous-Time Bandpass $\Delta\Sigma$ ADC Centered at 2 GHz for Direct Sampling Receivers
This paper presents a 40-GS/s continuous-time bandpass DeltaSigma analog-to-digital converter centered at 2 GHz for wireless base… 
2005
2005
A 4-bit 5 GS/s flash A/D converter in 0.18 /spl mu/m CMOS
A 4-bit 5 GS/s flash analog-to-digital converter (ADC) is designed and simulated in a 0.18 /spl mu/m CMOS technology. Low-swing… 
1999
1999
A 75 mW 10 b 20 MSample/s CMOS subranging ADC with 59 dB SNDR
In a two-step CMOS subranging ADC (CSA), a coarse comparator bank determines which subset of fine reference taps from a resistor… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)