• Publications
  • Influence
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
TLDR
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Expand
  • 826
  • 98
  • PDF
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
TLDR
We report a 10b SAR ADC that uses binary-scaled DAC networks for settling error compensation. Expand
  • 244
  • 19
  • PDF
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications
TLDR
This paper presents an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. Expand
  • 111
  • 13
  • PDF
A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS
  • Chun-Cheng Liu
  • Engineering, Computer Science
  • IEEE Asian Solid-State Circuits Conference (A…
  • 1 November 2014
TLDR
This paper presents a low-cost SAR ADC design for IEEE 802.11ac applications. Expand
  • 51
  • 12
  • PDF
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
TLDR
This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Expand
  • 88
  • 8
  • PDF
28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter
TLDR
We present an energy-efficient noise-shaping SAR ADC that suppresses the comparison and quantization noise in signal BW using a simple cascaded FIR-IIR filter, which obviates the need for a power-hungry low-noise comparator or high-performance op-amp. Expand
  • 45
  • 8
A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS
TLDR
This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. Expand
  • 56
  • 7
  • PDF
A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS
TLDR
This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. Expand
  • 103
  • 5
  • PDF
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count
TLDR
This paper reports an asynchronous binary-search analog-to-digital converter (ADC) with reference range prediction that achieves the balance between power consumption and operation speed. Expand
  • 49
  • 4
  • PDF
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS
TLDR
This paper reports a 5b asynchronous binary-search ADC with reference-range prediction. Expand
  • 39
  • 4
  • PDF