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Dual loop
Dual-loop is a method of electrical circuit termination used in electronic security applications, particularly modern intruder alarms. It is called…
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Unbiased Finite-Memory Digital Phase-Locked Loop
S. You
,
J. Pak
,
C. Ahn
,
P. Shi
,
M. Lim
IEEE Transactions on Circuits and Systems - II…
2016
Corpus ID: 11078367
Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance…
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2015
2015
A fully analog calibration technique for phase and gain mismatches in image-reject receivers
Ali Nikoofard
,
Siavash Kananian
,
A. Fotowat-Ahmady
2015
Corpus ID: 62728403
2008
2008
10 GHz dual loop opto-electronic oscillator without RF-amplifiers
Weimin Zhou
,
O. Okusaga
,
C. Nelson
,
D. Howe
,
G. Carter
SPIE OPTO
2008
Corpus ID: 97435218
We report the first demonstration of a 10 GHz dual-fiber-loop Opto-Electronic Oscillator (OEO) without RF-amplifiers. Using a…
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2008
2008
Dual-Wavelength Packets Buffering in Dual-Loop Optical Buffer
C. Tian
,
Chongqing Wu
,
Zhengyong Li
,
N. Guo
IEEE Photonics Technology Letters
2008
Corpus ID: 10174524
We demonstrated 10-Gb/s dual-wavelength packets buffering in a dual-loop optical buffer with a semiconductor optical amplifier…
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2006
2006
Dynamic current sharing analyses for multiphase buck VRs
Juanjuan Sun
,
Y. Qiu
,
Ming Xu
,
F. Lee
Twenty-First Annual IEEE Applied Power…
2006
Corpus ID: 44874838
For high-control-bandwidth multiphase buck voltage regulators, this paper addresses the issue of dynamic current sharing among…
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2006
2006
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL
Dong-Uk Lee
,
Hyun-Woo Lee
,
+10 authors
J. Kih
IEEE International Solid-State Circuits…
2006
Corpus ID: 12038734
A series pipelined CAS latency control with voltage-controlled delay line that extends maximum data rate to 2.5Gb/s/pin at 1.7V…
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2006
2006
A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver
M. He
,
J. Poulton
IEEE Journal of Solid-State Circuits
2006
Corpus ID: 35482569
A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR…
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2006
2006
An integrated 0.35mum CMOS optical receiver with clock and data recovery circuit
Yi-Ju Chen
,
M. Plessis
Microelectronics Journal
2006
Corpus ID: 7962326
Highly Cited
2001
Highly Cited
2001
A dual-loop delay-locked loop using multiple voltage-controlled delay lines
Yeon-Jae Jung
,
Seungwooi Lee
,
Daeyun Shim
,
Wonchan Kim
,
Changhyun Kim
,
Sooin Cho
IEEE J. Solid State Circuits
2001
Corpus ID: 16989906
This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple…
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1978
1978
Dual-Loop Model of the Human Controller
R. Hess
1978
Corpus ID: 61852052
A dual-loop model of the human controller in single-axis compensatory tracking tasks is introduced. This model possesses an inner…
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