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Digital timing diagram
Known as:
Timing diagram
, Timing diagram (electronics)
A digital timing diagram is a representation of a set of signals in the time domain. A timing diagram can contain many rows, usually one of them…
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Related topics
Related topics
7 relations
Byte
Datasheet
Hazard (logic)
High impedance
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Design and implementation of sorting algorithms based on FPGA
A. F. M. Fahad Alif
,
S. Islam
,
Polash Deb
International Conference on Computer…
2019
Corpus ID: 213183528
Analysis of the efficiency of sorting algorithms most often bound up to software simulation. In practical field real time…
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2007
2007
Sensing Workload Scheduling in Sensor Networks Using Divisible Load Theory
Xiaolin Li
,
Xinxin Liu
,
Hui Kang
IEEE GLOBECOM - IEEE Global Telecommunications…
2007
Corpus ID: 9554394
This paper presents scheduling strategies for sensing workload in wireless sensor networks using Divisible Load Theory (DLT…
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2000
2000
Model Checking Synchronous Timing Diagrams
N. Amla
,
E. Emerson
,
R. Kurshan
,
Kedar S. Namjoshi
Formal Methods in Computer-Aided Design
2000
Corpus ID: 16381128
Model checking is an automated approach to the formM verification of hardware and software. To allow model checking tools to be…
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2000
2000
Formalizing Timing Diagrams as Causal Dependencies for Verification Purposes
J. Fischer
,
Stefan Conrad
International Conference on Integrated Formal…
2000
Corpus ID: 45186228
In this paper we investigate timing diagrams as a means to specify causal dependencies. We introduce a stylized graphical…
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2000
2000
A low jitter dual loop DLL using multiple VCDLs with a duty cycle corrector
Yeon-Jae Jung
,
Seung Wook Lee
,
Daeyun Shim
,
Wonchan Kim
,
Changhyun Kim
,
Sooin Cho
2000
Corpus ID: 6424628
A low jitter dual loop DLL with multiple VCDLs has been developed. This DLL whose locking range is 150-600 MHz, allows unlimited…
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1999
1999
Efficient Decompositional Model Checking for Regular Timing Diagrams
Nina Amlay
,
Allen Emersonz
,
Kedar S. Namjoshix
Conference on Correct Hardware Design and…
1999
Corpus ID: 7155818
Timing diagrams are widely used in industrial practice to express precedence and timing relationships amongst a collection of…
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Review
1998
Review
1998
The ICOS Synthesis Environment
Karsten Lüth
Formal Techniques in Real-Time and Fault-Tolerant…
1998
Corpus ID: 17454078
This paper presents an overview of the ICOS system, a design environment for control-dominated reactive systems, which is based…
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1998
1998
Synthesis of interface controllers from timing diagram specifications
A. El-Aboudi
,
E. Aboulhamid
,
E. Cerny
Proceedings of the IEEE Custom Integrated…
1998
Corpus ID: 6795214
We present a method for verifying the realizability of a timing diagram, ensuring the synthesis of the underlying interface is…
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1993
1993
Introducing structure into behavioural descriptions obtained from timing diagram specifications
Wolf-Dieter Tiedemann
,
S. Lenk
,
C. Grobe
,
W. Grass
Microprocessing and Microprogramming
1993
Corpus ID: 26771562
1992
1992
Formalized timing diagrams
G. Borriello
[] Proceedings The European Conference on Design…
1992
Corpus ID: 54019162
Traditionally, the timing behavior of digital circuits has been described using timing or waveform diagrams. These diagrams…
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