Skip to search formSkip to main contentSkip to account menu

Digital signal processor

Known as: Processor, DSP Chip, Digital signals processor 
A digital signal processor (DSP) is a specialized microprocessor (or a SIP block), with its architecture optimized for the operational needs of… 
Wikipedia (opens in a new tab)

Related topics

Related topics

50 relations
AMD Radeon Rx 200 seriesAVR32Adaptive filterAdreno

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2013
Highly Cited
2013
InP Mach–Zehnder Modulator Platform for 10/40/100/200-Gb/s Operation
We describe the design and performance of a wavelength-flexible modulator platform based on multiple quantum well epitaxy on InP… 
Highly Cited
2010
Highly Cited
2010
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber
This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR… 
Highly Cited
2006
Highly Cited
2006
A New Torque and Flux Controller for Direct Torque Control of Induction Machines
This paper presents the implementation of a high-performance direct torque control (DTC) of induction machines drive. DTC has two… 
Highly Cited
2005
Highly Cited
2005
LusSy: a toolbox for the analysis of systems-on-a-chip at the transactional level
We describe a toolbox for the analysis of systems-on-a-chip described in SystemC at the transactional level. The tools are able… 
Highly Cited
2005
Highly Cited
2005
Embedded Type-2 FLC for Real-Time Speed Control of Marine and Traction Diesel Engines
Marine propulsion and traction diesel engines operate in highly dynamic and uncertain environments. The current speed controllers… 
Highly Cited
2001
Highly Cited
2001
A 2.7V CMOS dual-mode baseband filter for PDC and WCDMA
An 5th order analog CMOS RC-opamp baseband filter for a dual-mode cellular phone receiver was designed with maximum component… 
Highly Cited
2001
Highly Cited
2001
On the complexity of turbo decoding algorithms
  • P.H. Wu
  • IEEE VTS 53rd Vehicular Technology Conference…
  • 2001
  • Corpus ID: 62165459
We evaluate the computational complexity of several turbo decoding algorithms: log maximum a posteriori (log-MAP), maximum log… 
Highly Cited
1999
Highly Cited
1999
A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP
A MIMD multiprocessor DSP chip containing four 64-b processing elements (PEs) interconnected by a 128-b pipelined split… 
Highly Cited
1997
Highly Cited
1997
Reconfigurable processing: the solution to low-power programmable DSP
One of the most compelling issues in the design of wireless communication components is to keep power dissipation between bounds… 
Highly Cited
1988
Highly Cited
1988
Programmable DSP architectures. II
For pt.I see ibid., vol.5, no.4, p.4-19, Oct. 1988. Three distinct techniques are used for dealing with pipelining, namely… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)