SHAPES:: a tiled scalable software hardware architecture platform for embedded systems

@article{Paolucci2006SHAPESAT,
  title={SHAPES:: a tiled scalable software hardware architecture platform for embedded systems},
  author={Pier Stanislao Paolucci and Ahmed Amine Jerraya and Rainer Leupers and Lothar Thiele and Piero Vicini},
  journal={Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06)},
  year={2006},
  pages={167-172}
}
Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" processing tiles connected by "short wires". A typical SHAPES tile contains a VLIW floating-point DSP, a RISC, a DNP (Distributed Network Processor), distributed on chip memory, the POT (a set of Peripherals On Tile) plus an interface for DXM (Distributed External Memory). The SHAPES routing… CONTINUE READING
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