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Digital delay generator
Known as:
Digital delay generators
, Digital-to-time converter
, Dual-trigger digital delay generator
A digital delay generator (also known as digital-to-time converter) is a piece of electronic test equipment that provides precise delays for…
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Related topics
Related topics
8 relations
Channel (communications)
Crystal oscillator
Data acquisition
Graphical user interface
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
A Fully Digital Phase Modulator With a Highly Linear Phase Calibration Loop for Wideband Polar Transmitters
Yong-Chang Choi
,
Mauricio Velazquez Lopez
,
Sounghun Shin
,
Sang-Sun Yoo
,
Hyung-Joun Yoo
IEEE Transactions on Circuits and Systems - II…
2019
Corpus ID: 59554375
This brief presents a digital phase modulator for wideband polar transmitters. It adopts a digital-to-time converter (DTC) and a…
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2018
2018
A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs
Tuan Minh Vo
,
C. Samori
,
S. Levantino
International Symposium on Circuits and Systems
2018
Corpus ID: 53083930
In today's fractional-N phase-locked loops, digital-to-time converters are commonly used to cancel the quantization noise of the…
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2017
2017
Power-efficient, gate-based Digital-to-Time converter in CMOS
Oystein Bjorndal
,
T. Lande
International Symposium on Circuits and Systems
2017
Corpus ID: 28931463
A Digital-to-Time converter (DTC) based on static CMOS multiplexers is presented, achieving a time resolution of 65 ps consuming…
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2017
2017
Development of Analytical Behavioral Models for Digitally Controlled Edge Interpolator (DCEI) based Digital-to-Time Converter (DTC) Circuits
Sebastian Sievert
2017
Corpus ID: 201129908
Digital-to-time converter (DTC) circuits enable various applications in the area of frequency synthesis. Phase interpolator (PI…
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2016
2016
19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection
Somnath Kundu
,
Bongjin Kim
,
C. Kim
IEEE International Solid-State Circuits…
2016
Corpus ID: 9431197
Multiplying delay-locked loops (MDLLs) are gaining popularity due to their superior noise performance over conventional phase…
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2013
2013
A spur cancellation technique for MDLL-based frequency synthesizers
Giovanni Marzin
,
Andrea Fenaroli
,
G. Marucci
,
S. Levantino
,
C. Samori
,
A. Lacaita
International Symposium on Circuits and Systems
2013
Corpus ID: 32480188
This paper introduces a technique for suppressing the effect of deterministic jitter in phase-locked loops based on multiplying…
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2013
2013
Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL
J. Zhuang
,
R. Staszewski
European Conference on Circuit Theory and Design
2013
Corpus ID: 16603027
We propose a gain estimation technique of a digital-to-time converter (DTC) and a time-to-digital converter (TDC) intended for an…
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2012
2012
A 12-bit digital-to-time converter (DTC) with sub-ps-level resolution using current DAC and differential switch for time-to-digital converter (TDC)
S. Alahdab
,
A. Mantyniemi
,
J. Kostamovaara
IEEE International Instrumentation and…
2012
Corpus ID: 22387680
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital…
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2010
2010
A 12-bit digital-to-time converter (DTC) for time-to-digital converter (TDC) and other time domain signal processing applications
S. Al-Ahdab
,
A. Mantyniemi
,
J. Kostamovaara
Nordic Microelectronics Event
2010
Corpus ID: 6747003
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital…
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2009
2009
A fully digital polar transmitter using a digital-to-time converter for high data rate system
Yong-Chang Choi
,
Sang-Sun Yoo
,
Hyung-Joun Yoo
International Symposium on Radio-Frequency…
2009
Corpus ID: 41206620
Digital polar transmitter is suitable for high integrated and power efficient implementation. In order to support high data rate…
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