R. Staszewski

Publications
Influence

All-digital frequency synthesizer in deep-submicron CMOS

R. Staszewski, P. Balsara
Computer Science
2006

PREFACE. 1 INTRODUCTION. 1.1 Frequency Synthesis. 1.1.1 Noise in Oscillators. 1.1.2 Frequency Synthesis Techniques. 1.2 Frequency Synthesizer as an Integral Part of an RF Transceiver. 1.2.1… Expand

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

R. Staszewski, Sudheer Vemulapalli, Prasant Vallur, John L. Wallberg, P. Balsara
Engineering, Computer Science
IEEE Transactions on Circuits and Systems II…
13 March 2006

We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS, which is the finest logic-level regenerative timing in CMOS. Expand

Phase-domain all-digital phase-locked loop

R. Staszewski, P. Balsara
Engineering, Computer Science
IEEE Transactions on Circuits and Systems II…
14 March 2005

A fully digital frequency synthesizer for RF wireless applications has recently been proposed. Expand

Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process

R. Staszewski, D. Leipold, Khurram Muhammad, P. Balsara
Engineering
17 November 2003

A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning… Expand

A first multigigahertz digitally controlled oscillator for wireless applications

R. Staszewski, C. Hung, D. Leipold, P. Balsara
Engineering
3 November 2003

A novel digitally controlled oscillator (DCO) architecture for multigigahertz wireless RF applications, such as short-range wireless connectivity or cellular phones, is proposed and demonstrated. It… Expand

All-Digital PLL With Ultra Fast Settling

R. Staszewski, P. Balsara
Engineering, Computer Science
IEEE Transactions on Circuits and Systems II…
20 February 2007

We present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise. Expand

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

W. Wu, R. Staszewski, J. Long
Engineering, Computer Science
IEEE Journal of Solid-State Circuits
10 February 2014

A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. Expand

A Class-F CMOS Oscillator

M. Babaie, R. Staszewski
Engineering, Computer Science
IEEE Journal of Solid-State Circuits
7 August 2013

An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. Expand

Event-driven Simulation and modeling of phase noise of an RF oscillator

R. Staszewski, C. Fernando, P. Balsara
Computer Science
IEEE Transactions on Circuits and Systems I…
11 April 2005

A novel simulation technique that uses an event-driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated. Expand

Direct RF sampling mixer with recursive filtering in charge domain

K. Muhammad, R. Staszewski
Engineering, Computer Science
IEEE International Symposium on Circuits and…
23 May 2004

We present a direct RF sampling technique in which an input RF signal is converted to a current waveform, gated and integrated on a sampling capacitor. Expand

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