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Die shrink

Known as: Semiconductor scaling, 55 nanometer, 40 nanometer 
The term die shrink (sometimes optical shrink or process shrink) refers to a simple semiconductor scaling of semiconductor devices, mainly… Expand
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Papers overview

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Highly Cited
2014
Highly Cited
2014
This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in… Expand
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Highly Cited
2014
Highly Cited
2014
A software-defined radio receiver is presented, operating from 400 MHz to 6 GHz. The split front-end architecture has a low-band… Expand
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Highly Cited
2014
Highly Cited
2014
This paper presents a power-efficient 80 MS/s, 11 bit ENOB ADC. It is realized in 28 nm CMOS and is based on two interleaved… Expand
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2014
2014
CMOS technology scaling has enabled the design of high speed and efficient digital circuits. However, the continued scaling is… Expand
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Highly Cited
2009
Highly Cited
2009
Research on mudrock attributes has increased dramatically since shale-gas systems have become commercial hydrocarbon production… Expand
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Highly Cited
2006
Highly Cited
2006
We develop detailed area and energy models for on-chip interconnection networks and describe tradeoffs in the design of efficient… Expand
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Highly Cited
2004
Highly Cited
2004
The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and… Expand
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Highly Cited
2003
Highly Cited
2003
Silicon technology has progressed over the last several years from a digitally oriented technology to one well suited for… Expand
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Highly Cited
2003
Highly Cited
2003
The merger of nanoscale devices with flexible, low cost plastics could enable a broad spectrum of electronic and photonic… Expand
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Highly Cited
2003
Highly Cited
2003
Novel millable polyurethane (PU)/organoclay nanocomposites have been successfully prepared by conventional transformation… Expand
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