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Die shrink
Known as:
Semiconductor scaling
, 55 nanometer
, 40 nanometer
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The term die shrink (sometimes optical shrink or process shrink) refers to a simple semiconductor scaling of semiconductor devices, mainly…
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Related topics
Related topics
31 relations
Apple mobile application processors
Arrandale
Athlon
Baikal CPU
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170$^{\circ}$ C
Y. Taito
,
T. Kono
,
+5 authors
T. Yamauchi
IEEE Journal of Solid-State Circuits
2016
Corpus ID: 23597256
First-ever 28 nm embedded split-gate MONOS (SG-MONOS) flash macros have been developed to increase memory capacity embedded in…
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2015
2015
Steamroller Module and Adaptive Clocking System in 28 nm CMOS
Kathryn Wilcox
,
Robert Cole
,
+12 authors
Jonathan White
IEEE Journal of Solid-State Circuits
2015
Corpus ID: 12482137
This work describes the physical design implementation of the AMD “Steamroller” module and adaptive clocking system that are both…
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2015
2015
Alpha soft error rate of FDSOI 28 nm SRAMs: Experimental testing and simulation analysis
V. Malherbe
,
G. Gasiot
,
Dimitri Soussan
,
Aurelien Patris
,
J. Autran
,
P. Roche
IEEE International Reliability Physics Symposium
2015
Corpus ID: 5975851
We report on soft error rate measurements on 28 nm commercial FDSOI SRAM bitcells under alpha irradiation. The technology proves…
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2015
2015
A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz
G. Radulov
,
P. Quinn
,
A. Roermund
IEEE Transactions on Very Large Scale Integration…
2015
Corpus ID: 12350262
This brief presents a 7-GS/s 6-bit current-steering digital-to-analog converter (DAC) in 28-nm CMOS for VLSI System On Chip I/O…
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2014
2014
Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI
F. Abouzeid
,
A. Bienfait
,
+6 authors
P. Roche
IEEE Journal of Solid-State Circuits
2014
Corpus ID: 6889906
This work presents a method for the design and characterization of a scalable ultra-wide voltage range static random access…
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2011
2011
Through-Silicon via Technology for 3D IC
E. Beyne
2011
Corpus ID: 108244206
Three-dimensional (3D) integration complements semiconductor scaling in enabling higher integration density as well as…
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Review
2011
Review
2011
Study on TSV with new filling method and alloy for advanced 3D-SiP
Akihiro Tsukada
,
Ryohei Sato
,
+5 authors
Hidenori Murata
Electronic Components and Technology Conference
2011
Corpus ID: 25128391
We focus on 3D-SiP using TSV's as one possible breakthrough method that can overcome semiconductor scaling limits. To this point…
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2008
2008
Die-to-database mask inspection with variable sensitivity
H. Tsuchiya
,
M. Tokita
,
T. Nomura
,
Tadao Inoue
Photomask Japan
2008
Corpus ID: 110685035
The cost of mask is increasing dramatically along with the continuous semiconductor scaling. ASET started a 4-year project to…
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Highly Cited
2003
Highly Cited
2003
New Millable Polyurethane/Organoclay Nanocomposite: Preparation, Characterization and Properties
J. K. Mishra
,
Il Kim
,
C. Ha
2003
Corpus ID: 54827905
Novel millable polyurethane (PU)/organoclay nanocomposites have been successfully prepared by conventional transformation…
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1999
1999
Preparation of zinc oxide-dispersed silver particles by spray pyrolysis of colloidal solution
Y. Kang
,
Seung-Bin Park
1999
Corpus ID: 137111754
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