Die shrink

Known as: Semiconductor scaling, 55 nanometer, 40 nanometer 
The term die shrink (sometimes optical shrink or process shrink) refers to a simple semiconductor scaling of semiconductor devices, mainly… (More)
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Papers overview

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Highly Cited
2014
Highly Cited
2014
This paper presents the implementation details and silicon results of a 3 GHz dual-core ARM Cortex TM -A9 (A9) manufactured in… (More)
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2014
2014
A software-defined radio receiver is presented, operating from 400 MHz to 6 GHz. The split front-end architecture has a low-band… (More)
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2014
2014
This paper presents a power-efficient 80 MS/s, 11-bit ENOB ADC. It is realized in 28 nm CMOS and is based on two interleaved… (More)
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2014
2014
Extracting information about MCUs from SEU data sets can be a challenge without physical layout information. Many modern static… (More)
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2014
2014
A reconfigurable heterogeneous 3D-IC is assembled from two 28 nm FPGA die with 580 k logic cells and two 65 nm mixed signal die… (More)
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2013
2013
Alpha, neutron, and heavy-ion single-event measurements were performed on both high-performance and hardened flip-flop designs in… (More)
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2013
2013
High-speed signaling over high density interconnect on organic package substrates or silicon interposers offers an attractive… (More)
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Highly Cited
2011
Highly Cited
2011
Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical… (More)
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Highly Cited
2009
Highly Cited
2009
Research on mudrock attributes has increased dramatically since shale-gas systems have become commercial hydrocarbon production… (More)
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Highly Cited
2004
Highly Cited
2004
The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and… (More)
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