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Die shrink

Known as: Semiconductor scaling, 55 nanometer, 40 nanometer 
The term die shrink (sometimes optical shrink or process shrink) refers to a simple semiconductor scaling of semiconductor devices, mainly… 
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
First-ever 28 nm embedded split-gate MONOS (SG-MONOS) flash macros have been developed to increase memory capacity embedded in… 
2015
2015
This work describes the physical design implementation of the AMD “Steamroller” module and adaptive clocking system that are both… 
2015
2015
We report on soft error rate measurements on 28 nm commercial FDSOI SRAM bitcells under alpha irradiation. The technology proves… 
2015
2015
This brief presents a 7-GS/s 6-bit current-steering digital-to-analog converter (DAC) in 28-nm CMOS for VLSI System On Chip I/O… 
2014
2014
This work presents a method for the design and characterization of a scalable ultra-wide voltage range static random access… 
2011
2011
Three-dimensional (3D) integration complements semiconductor scaling in enabling higher integration density as well as… 
Review
2011
Review
2011
We focus on 3D-SiP using TSV's as one possible breakthrough method that can overcome semiconductor scaling limits. To this point… 
2008
2008
The cost of mask is increasing dramatically along with the continuous semiconductor scaling. ASET started a 4-year project to… 
Highly Cited
2003
Highly Cited
2003
Novel millable polyurethane (PU)/organoclay nanocomposites have been successfully prepared by conventional transformation…