A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170$^{\circ}$ C

  title={A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170\$^\{\circ\}\$ C},
  author={Yasuhiko Taito and Takashi Kono and Masaya Nakano and Tomoya Saito and Takashi Ito and Kenji Noguchi and Hideto Hidaka and Tadaaki Yamauchi},
  journal={IEEE Journal of Solid-State Circuits},
First-ever 28 nm embedded split-gate MONOS (SG-MONOS) flash macros have been developed to increase memory capacity embedded in micro controller units and to improve performance over wide junction temperature range from -40°C to 170 °C as demanded strongly in automotive uses. [] Key Method Temperature-adaptive step pulse erase control (TASPEC) improves the TDDB lifetime of dielectric films between metal interconnect layers by three times. TASPEC is particularly useful for a data flash macro with one million…
A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application
This paper presents the first embedded multi-level cell flash memory macro for automotive application manufactured in 28 nm technology that employs a robust time-domain voltage sensing scheme with ramped gate cell biasing to achieve low latency combined with increased fault tolerance.
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity
The design and implementation of an 80-kb logic-embedded non-volatile multi-time programmable memory (MTPM) with no added process complexity is described and high-temperature stress results show a projected data retention of 10 years at 125 °C.
A 58-nm 2-Gb MLC “B4-Flash” Memory with Flexible Multisector Architecture
This paper proves that B4-Flash can be a candidate for various applications which need both fast rewrite speed and fast random access as a fast rewritable NOR-type flash with MLC capability and scalability.
A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D
A 28-nm 600-MHz automotive flash MCU for vehicle control integrates a virtualization-assisted processor (VAP) for functional safety, a built-in self-test in the field (field-BIST) at a sleep resume (SR) BIST forfunctional safety, and a serial gigabit media independent interface (SGMII) for the in-vehicle network.
Shared-Write-Channel-Based Device for High-Density Spin-Orbit-Torque Magnetic Random-Access Memory
Spin-orbit-torque (SOT) devices are promising candidates for the future magnetic memory landscape, as they promise high endurance, low read disturbance, and low read error, in comparison with
Improvement of Cell’s Performance for Low Power Self-Aligned Split-Gate SONOS Memory Device
  • Jun Hu, Zhaozhao Xu, W. Qian
  • Engineering
    2019 China Semiconductor Technology International Conference (CSTIC)
  • 2019
A novel low power split-gate SONOS is proposed to improve cell’s performance. The self-aligned fabrication steps of this novel device are presented and the characteristic is demonstrated. It was
Investigation and three implementations for low power self-aligned 1.5-T SONOS flash device
  • Zhaozhao Xu, Donghua Liu, W. Qian
  • Engineering, Computer Science
    2018 China Semiconductor Technology International Conference (CSTIC)
  • 2018
Two novel implementations (N+&P+-Polysilicon Memory/Memory1 and Memory-First/Memory2) and a conventional way (Memory-Last/Memory3) for low power self-aligned 1.5-T SONOS are demonstrated and characteristic of them are compared and investigated.
Fabrication and Characterization of A Novel Fully Self-Aligned Split-Gate Sonos Memory Device
  • Zhaozhao Xu, Jun Hu, W. Qian
  • Engineering
    2020 China Semiconductor Technology International Conference (CSTIC)
  • 2020
A novel low-power fully self-aligned split-gate silicon-oxide-nitride-oxide-silicon (SONOS) flash memory with “memory-last” configuration has been fabricated for the first time at 90-nm node.
Development of 2T-SONOS Cell Using a Contamination-Free Process Integration for a Highly Reliable Code Storage eNVM
By correlating high-temperature retention bake results with technology computer-aided design simulations, it can understand long-term charge redistribution behavior inside trap nitride, which is significantly different from floating gate type NVM.
A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications
The proposed ePCM features 18-ns random access time with improved robustness against resistance drift and the word modify time under 32-cell programming parallelism was kept as low as 20 <inline-formula> <tex- math notation="LaTeX">$\mu \text{s}$ </tex-math></inline- formula>, thanks to enhanced programming circuits.


40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data
  • T. Kono, T. Ito, T. Yamauchi
  • Computer Science
    2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
  • 2013
This paper presents 40nm eFlash macros for automotive with a 40nm SG- MONOS cell scaled to the next generation of SG-MONOS and a fast random-read-access and the developed sense amplifier.
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate
A novel 3 volts-only, small sector erase, high density flash E/sup 2/PROM
A split gate Flash E/sup 2/PROM memory cell with Fowler-Nordhiem tunneling erase, and high efficiency hot electron programming is presented, and it is shown that the cell is immune to read and write disturb conditions.
7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage
An enterprise-grade SSD with TLC (3b/cell) NAND Flash is presented with three techniques that achieve high speed and high reliability. Quick low-density parity-check (LDPC) reduces the read latency
A 512 kB MONOS type flash memory module embedded in a microcontroller
  • T. Tanaka, H. Tanikawa, M. Hiraki
  • Computer Science
    2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)
  • 2003
A new memory cell structure enables the whole read path in the module to be composed of low voltage transistors that are the same as those used in the CPU core, and therefore achieves compact layout of peripheral circuits.
Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and below
This work presents recent results on Secondary Electron flash memory, and contrasts this approach to standard for scaled, low power mass storage applications.
A 28 nm Embedded SG-MONOS Flash Macro for Automotive Achieving 200 MHz Read Operation and 2.0 MB/s Write Throughput at Tj of 170 C
  • Proc. ISSCC Dig. Tech. Papers, pp. 132–133, 2015.
  • 2015
A 65 nm 4 MB Embedded Flash Macro for Automotive Achieving a Read Throughput of 5.7 GB/s and a Write Throughput of 1.4 MB/s
  • Proc. ESSCIRC, pp. 193–196, 2013.
  • 2013