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Delta delay

In VHDL simulations, all signal assignments occur with some infinitesimal delay, known as delta delay. Technically, delta delay is of no measurable… 
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2009
2009
Logic Cell modeling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear… 
2003
2003
The Enhanced Variable Rate Codec (EVRC) is a standard for the Speech Service Option 3 for Wideband Spread Spectrum Digital System… 
2002
2002
  • Sumit Ghosh
  • 2002
  • Corpus ID: 7695198
This paper has traced the VHDL architects' journey into the world of delta delay including the original need for zero delay usage… 
2002
2002
This paper will describe an evaluation flow for crosstalk analysis, repair and prevention using PrimeTime-SI and Mars-Xtalk… 
Review
2002
Review
2002
  • 2002
  • Corpus ID: 264752813
1997
1997
Addresses the problem of online, writer-independent, unconstrained handwriting recognition. Based on hidden Markov models (HMM… 
Review
1995
Review
1995
This tutorial paper gives a functional semantics for delta-delay VHDL, i.e. VHDL restricted to zero-delay signal assignments. In… 
Review
1995
Review
1995
This paper presents from the users point of view the automatic veri cation of nontrivial liveness properties for a reactive… 
1994
1994
Code excited linear prediction (CELP) is a voice-coding technique developed by AT&T Bell Labs and the U.S. Department of Defense… 
1993
1993
The concept of delta delay - simulation step seen as an infinitesimal delay - is the VHDL artifice to enforce causality in…