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Cray XD1
The Cray XD1 was an entry-level supercomputer range, made by Cray Inc. The XD1 uses AMD Opteron 64-bit CPUs, and utilizes the Direct Connect…
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Related topics
Related topics
10 relations
Central processing unit
Field-programmable gate array
Heterogeneous computing
HyperTransport
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Integrated Design Environment for Reconfigurable HPC
L. Janin
,
Shoujie Li
,
D. Edwards
International Workshop on Applied Reconfigurable…
2010
Corpus ID: 285038
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time…
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2009
2009
A context switching streaming memory architecture to accelerate a neocortex model
Christopher N. Vutsinas
,
T. Taha
,
Kenneth L. Rice
Microprocessors and microsystems
2009
Corpus ID: 15731667
2008
2008
Speeding Genomic Searches over 1000X Over a Single Opteron Using Multiple FPGAs on a Cray XD1
O. Storaasli
,
D. Strenski
,
P. LoCascio
2008
Corpus ID: 59783617
Our CUG07 paper demonstrated the Cray Smith-Waterman FPGA design could achieve 50-100X speedup over a single Opteron. This paper…
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2008
2008
A Case Study of Hardware/Software Partitioning of Traffic Simulation on the Cray XD1
J. Tripp
,
M. Gokhale
,
A. Hansson
IEEE Transactions on Very Large Scale Integration…
2008
Corpus ID: 14608253
Scientific application kernels mapped to reconfigurable hardware have been reported to have 10times to 100times speedup over…
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2008
2008
Using Mitrion-C to Implement Floating-Point Arithmetic on a Cray XD1
K. K. Liu
,
C. B. Cameron
,
A. Sarkady
DoD HPCMP Users Group Conference
2008
Corpus ID: 10424011
Field-Programmable Gate Arrays (FPGAs) are of interest to the high performance computing (HPC) computing community because they…
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2008
2008
Portable library development for reconfigurable computing systems: A case study
P. Saha
,
E. El-Araby
,
+7 authors
D. Buell
Parallel Computing
2008
Corpus ID: 40399468
2007
2007
Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor
Volker Hampel
,
P. Sobe
,
E. Maehle
Euromicro Symposium on Digital Systems Design
2007
Corpus ID: 2577244
In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which…
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2006
2006
Optimizing Application Performance on Cray Systems with PGI Compilers and Tools
D. Miles
,
Brent Leback
2006
Corpus ID: 59797571
PGI Fortran, C and C++ compilers and tools are available on most Cray XT3 and Cray XD1 systems. Optimizing performance of the AMD…
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2006
2006
USURP: A Standard for Design Portability in Reconfigurable Computing
J. Greco
,
B. Holland
,
I. Troxel
,
G. Barfield
,
V. Aggarwal
,
A. George
2006
Corpus ID: 16006834
The proprietary nature of FPGA platforms has been a hin- drance to developer and user productivity since the inception of recon…
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2005
2005
Reconfigurable computing aspects of the Cray XD1.
C. Ulmer
,
Ryan Hilles
,
D. Thompson
,
K. Hemmert
,
K. Underwood
2005
Corpus ID: 59699712
Reconfigurable Computing (RC) refers to the use of reconfigurable hardware devices to accelerate the computational performance of…
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