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Cray XD1

The Cray XD1 was an entry-level supercomputer range, made by Cray Inc. The XD1 uses AMD Opteron 64-bit CPUs, and utilizes the Direct Connect… 
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Related topics

Related topics

10 relations
Central processing unitField-programmable gate arrayHeterogeneous computingHyperTransport

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time… 
2010
2010
A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs
Recent advances in Field-Programmable Gate Array (FPGA) technology make reconfigurable computing using FPGAs an attractive… 
2009
2009
A context switching streaming memory architecture to accelerate a neocortex model
2009
2009
HASPRNG: Hardware Accelerated Scalable Parallel Random Number Generators
2008
2008
FPGA acceleration of a quantum Monte Carlo application
Highly Cited
2008
Highly Cited
2008
High-Performance Mixed-Precision Linear Solver for FPGAs
Compared to higher-precision data formats, lower-precision data formats result in higher performance for computational intensive… 
2008
2008
Speeding Genomic Searches over 1000X Over a Single Opteron Using Multiple FPGAs on a Cray XD1
Our CUG07 paper demonstrated the Cray Smith-Waterman FPGA design could achieve 50-100X speedup over a single Opteron. This paper… 
2008
2008
A Case Study of Hardware/Software Partitioning of Traffic Simulation on the Cray XD1
Scientific application kernels mapped to reconfigurable hardware have been reported to have 10times to 100times speedup over… 
2007
2007
Experiences with a FPGA-based Reed/Solomon Encoding Coprocessor
In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which… 
2005
2005
Reconfigurable computing aspects of the Cray XD1.
Reconfigurable Computing (RC) refers to the use of reconfigurable hardware devices to accelerate the computational performance of… 
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