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CoreConnect

Known as: PLB (disambiguation), Processor Local Bus 
IBM makes the CoreConnect bus available as a no-fee, no-royalty architecture to tool-vendors, core IP-companies, and chip-development companies. As… 
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Process design artifacts (e.g., process models, textual process descriptions and simulations) are increasingly used to provide… 
Highly Cited
2014
Highly Cited
2014
Visible light communication (VLC) systems using the indoor lighting system to also provide downlink communications require high… 
Highly Cited
2007
Highly Cited
2007
In a municipal solid waste management system, decreasing collection/hauling costs, which consist of 85 % of total disposal… 
Highly Cited
2005
Highly Cited
2005
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address… 
2005
2005
  • N. Kondratjew
  • Zeitschrift für Anatomie und…
  • 2005
  • Corpus ID: 42636545
Schon im Jahre 1921 habe ich in meiner Arbeit ,,Zur Methodik dcr makroskopischen elektiven F/~rbung des peripherischen… 
Highly Cited
2003
Highly Cited
2003
The effects of prior cold rolling of up to an 80 pct reduction in thickness on the sensitization-desensitization behavior of Type… 
2003
2003
Abstract : The focus of this thesis is the use of sound for communication by the North Atlantic right whale (Eubalaena glacialis… 
1998
1998
An even harmonic type direct conversion receiver (EH-DCR) has an advantage of suppressing a degradation of sensitivity caused by… 
Review
1985
Review
1985
  • A. Smith
  • International Symposium on Computer Architecture
  • 1985
  • Corpus ID: 12504280
The selection of the "best" parameters for a cache design, such as size, mapping algorithm, fetch algorithm, line size, etc., is…