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Complex programmable logic device
Known as:
CPLD
A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features…
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Altera Hardware Description Language
Altera Quartus
Application-specific integrated circuit
ArVid
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
Area and speed oriented synthesis of FSMs for PAL-based CPLDs
R. Czerwinski
,
D. Kania
Microprocessors and microsystems
2012
Corpus ID: 43424486
2011
2011
Generic Complex Programmable Logic Device ( CPLD ) Board
Nagaraj Hediyal
2011
Corpus ID: 18444163
The design and development of Generic Complex Programmable Logic Device (CPLD) Board is to emphasis on the reduction of the…
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2010
2010
Field programmable gate array (FPGA) implementation of novel complex PN-code-generator- based data scrambler and descrambler
G. M. Bhat
,
M. Mustafa
,
S. A. Parah
,
Javaid Ahmad
2010
Corpus ID: 61723944
A novel technique for the generation of complex and lengthy code sequences using low- length linear feedback shift registers…
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2006
2006
Measurement of ultrasonic displacement using complex programmable logic device
Zhang Hong-ping
2006
Corpus ID: 64095861
Based on ultrasound and using a complex programmable logic device(CPLD),precision measurement of displacement is studied.In this…
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2005
2005
A new phase-delay-free method to detect back EMF zero-crossing points for sensorless control of spindle motors
Quan Jiang
,
Chao Bi
,
Ruoyu Huang
IEEE transactions on magnetics
2005
Corpus ID: 7143054
This paper introduces a new rotor position detecting method for the sensorless control of spindle motors in hard disk drives. The…
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2005
2005
Embedded system design with FPGA using HDL (lessons learned and pitfalls to be avoided)
R. J. Duckworth
International Conference on Microelectronics…
2005
Corpus ID: 10773989
This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate…
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2004
2004
Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits
M. Stojcev
,
G. Djordjevic
,
T. Stankovic
Microelectronics and reliability
2004
Corpus ID: 11916601
2002
2002
A technology mapping algorithm for CPLD architectures
Shih-Liang Chen
,
TingTing Hwang
,
C. Liu
IEEE International Conference on Field…
2002
Corpus ID: 41086299
In this paper, we propose a technology mapping algorithm for CPLD architectures. Our algorithm proceeds in two phases: mapping…
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2001
2001
Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks
K. Yan
Proceedings of the ASP-DAC . Asia and South…
2001
Corpus ID: 22755402
In some modern FPGAs and CPLDs, PLA (programmable logic array)-style logic blocks can be used as the storage elements for…
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2000
2000
Decomposition-based synthesis and its application in PAL-oriented technology mapping
D. Kania
Proceedings of the 26th Euromicro Conference…
2000
Corpus ID: 27771370
Most CPLD architectures include PAL based logic blocks containing a limited number of terms connected to the individual output…
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