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Altera Quartus

Known as: Quartus II, Sopc builder 
Altera Quartus II is a programmable logic device design software produced by Altera. Quartus II enables analysis and synthesis of HDL designs, which… 
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Related topics

Related topics

14 relations
Altera Hardware Description LanguageComplex programmable logic deviceField-programmable gate arrayHardware description language

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Application of AES algorithm for data security in serial communication
One of the major problems in communication is the secure transportation of data over communication protocols. This paper presents… 
2015
2015
Low power wallace tree multiplier using modified full adder
Achieving high speed integrated circuits with low power consumption is a major concern for the VLSI circuit designers. Most… 
Highly Cited
2013
Highly Cited
2013
Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering
In order to protect FPGA designs against IP theft and related issues such as product cloning, all major FPGA manufacturers offer… 
2012
2012
Low power Wallace multiplier design based on wide counters
Multiplication is one of the most basic arithmetic operations. It is used in digital applications, central processing units, and… 
Highly Cited
2011
Highly Cited
2011
Design and Simulation of UART Serial Communication Module Based on VHDL
UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance… 
2010
2010
Design of Pipelined FFT Processor Based on FPGA
It is important to develop a high-performance FFT processor to meet the requirements of real time and low cost in many different… 
2009
2009
A Novel High-Speed Parallel Scheme for Data Sorting Algorithm Based on FPGA
Efficient data sorting is important for searching and optimization algorithms in high time demanding fields such as image and… 
2009
2009
Toward Automated ECOs in FPGAs
Engineering change orders (ECOs), which are used to apply late-stage specification changes and bug fixes, have become an… 
Highly Cited
2008
Highly Cited
2008
An efficient Modified Booth multiplier architecture
We present the design of an efficient multiplication unit. This multiplier architecture is based on radix 4 booth multiplier. In… 
Highly Cited
2005
Highly Cited
2005
Incorporating simulation and implementation into teaching computer organization and architecture
This paper describes the motivation, the realization, and the experience of incorporating simulation and hardware implementation… 
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