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Altera Quartus

Known as: Quartus II, Sopc builder 
Altera Quartus II is a programmable logic device design software produced by Altera. Quartus II enables analysis and synthesis of HDL designs, which… 
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Related topics

Related topics

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Altera Hardware Description LanguageComplex programmable logic deviceField-programmable gate arrayHardware description language

Papers overview

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2015
2015
Design and Implementation of Pulse Width Modulation Controller on FPGA using HDL
:The project is concerned with the design, synthesis, and the implementation of pulse width modulation (PWM) on FPGA. The project… 
2014
2014
Metody syntezy komparatorów z wykorzystaniem języka Verilog w środowisku Quartus II
2012
2012
Optimization of FIR digital filter using low power MAC
In the majority of digital signal processing (DSP) applications the critical operations are the multiplication and accumulation… 
2012
2012
Implementation of Chaos Synchronization on FPGA
Abstract A new method of achieving synchronization of chaotic systems on FPGA is proposed in this paper. We take Lorenz chaotic… 
2011
2011
Design and FPGA implementation of digital noise generator based on superposition of Gaussian process
Currently in the design of digital communication system, in order to detect the communication quality, plenty of tests need to be… 
2010
2010
Design of the CIC decimation filter based on SOPC Builder
This CIC (Cascaded integrator comb) decimation filter is widely applicable to reduce the data sampling rate in DDC (Digital Down… 
2009
2009
A Simplified FPGA Implementation Based on an Improved DES Algorithm
  • Li FuMing Pan
  • Third International Conference on Genetic and…
  • 2009
  • Corpus ID: 18969155
Recently, DES has been the most widely used symmetric block cipher for information security. But many powerful attacks, such as… 
2009
2009
FPGA Based Parallel Architectures for Normalized Cross-Correlation
As a similarity measure, normalized cross-correlation has found application in a broad range of image processing. A dedicated… 
2006
2006
A High Performance Parallel FIR Filters Generation Tool
This paper presents generation tool and performance results on a method to minimize the amount of hardware needed to implement a… 
2004
2004
Optimizing a high performance 32-bit processor for programmable logic
  • P. Metzgen
  • International Symposium on System-on-Chip…
  • 2004
  • Corpus ID: 25665104
Summary form only given. Altera's SOPC Builder Tool enables engineers to create tailor-made systems in an FPGA with a short…