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CoDel
Known as:
Controlled Delay
In network routing, CoDel (pronounced "coddle") for controlled delay is a scheduling algorithm for the network scheduler developed by Van Jacobson…
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Related topics
Related topics
17 relations
Active queue management
Bufferbloat
Data buffer
Explicit Congestion Notification
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Broader (1)
Network performance
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology
Hechen Wang
,
F. Dai
European Solid-State Circuits Conference
2017
Corpus ID: 10686958
This paper presents a time-to-digital (TDC) design with large detectable range and fine resolution, combining a ring TDC with a 2…
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2008
2008
A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector
R. Chang
,
Hou-Ming Chen
,
Po-Jen Huang
IEEE Transactions on Circuits and Systems Part 1…
2008
Corpus ID: 22082546
This paper presents a multiphase-output delay-locked loop (MODLL). The proposed phase/frequency detector (PFD) utilizes a new…
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2007
2007
Timing-driven row-based power gating
A. Sathanur
,
A. Pullini
,
L. Benini
,
A. Macii
,
E. Macii
,
M. Poncino
Proceedings of the international symposium on…
2007
Corpus ID: 17409210
In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a row-based granularity. In…
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2003
2003
An 8-bit 100-MHz CMOS linear interpolation DAC
Yijun Zhou
,
Jiren Yuan
IEEE J. Solid State Circuits
2003
Corpus ID: 61824621
An 8-bit 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It applies a time-interleaved…
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Highly Cited
2002
Highly Cited
2002
Low-jitter clock multiplication: a comparison between PLLs and DLLs
R. V. D. Beek
,
E. Klumperink
,
C. Vaucher
,
B. Nauta
2002
Corpus ID: 14038664
This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter…
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Highly Cited
2001
Highly Cited
2001
A dual-loop delay-locked loop using multiple voltage-controlled delay lines
Yeon-Jae Jung
,
Seungwooi Lee
,
Daeyun Shim
,
Wonchan Kim
,
Changhyun Kim
,
Sooin Cho
IEEE J. Solid State Circuits
2001
Corpus ID: 16989906
This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple…
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2001
2001
An 8-Bit, 100-MHz low glitch interpolation DAC
Yijun Zhou
,
Jiren Yuan
ISCAS . The IEEE International Symposium on…
2001
Corpus ID: 12923139
This paper describes an 8-Bit, 100-MHz current steering CMOS low glitch interpolation digital to analog converter (DAC). It…
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Highly Cited
1997
Highly Cited
1997
A 256 Mb SDRAM using a register-controlled digital DLL
Atsushi Hatakeyama
,
H. Mochizuki
,
+16 authors
M. Taguchi
IEEE International Solids-State Circuits…
1997
Corpus ID: 26955152
This 256 Mb synchronous DRAM with 1 ns clock access is stable against temperature, voltage, and process variation by use of an…
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1993
1993
Irreducible Error Performance of a Digital Portable Communication System in a Controlled Time-Dispersion Indoor Channel
I. Crohn
,
G. Schultes
,
R. Gahleitner
,
E. Bonek
IEEE J. Sel. Areas Commun.
1993
Corpus ID: 12187123
The authors investigated experimentally, analytically, and by simulation the irreducible errors such as error floor for high…
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Highly Cited
1983
Highly Cited
1983
Calculating te maximum mean data rate in local area networks
B. Stuck
Computer
1983
Corpus ID: 21016336
In February 1980 a group of people met in San Francisco, CA, USA, to form Project 802: Local Area Network Standards, sponsored by…
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