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CoDel
Known as:
Controlled Delay
In network routing, CoDel (pronounced "coddle") for controlled delay is a scheduling algorithm for the network scheduler developed by Van Jacobson…
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Related topics
Related topics
17 relations
Active queue management
Bufferbloat
Data buffer
Explicit Congestion Notification
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Broader (1)
Network performance
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2007
2007
Timing-driven row-based power gating
A. Sathanur
,
A. Pullini
,
L. Benini
,
A. Macii
,
E. Macii
,
M. Poncino
Proceedings of the international symposium on…
2007
Corpus ID: 17409210
In this paper we focus on leakage reduction through automatic insertion of sleep transistors using a row-based granularity. In…
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2006
2006
New Technique for Visualizing Microboiling Phenomena and Its Application to Water Pulse Heated by a Thin Metal Film
C. Avedisian
,
R. Cavicchi
,
M. Tarlov
2006
Corpus ID: 10971533
This article presents a laser strobe microscopy method for photographing fast transient microscale processes. The technique is…
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2006
2006
A Tunable CMOS UWB Pulse Generator
Hyunseok Kim
,
Y. Joo
,
Sungyong Jung
IEEE International Conference on Ultra-Wideband
2006
Corpus ID: 21155905
A tunable ultra-wideband (UWB) pulse generator is designed and simulated with standard 0.18 mum CMOS technology. By using a…
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Highly Cited
2005
Highly Cited
2005
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop
Hsiang-Hui Chang
,
Shen-Iuan Liu
IEEE Journal of Solid-State Circuits
2005
Corpus ID: 25695048
An all-digital cycle-controlled delay-locked loop (DLL) is presented to achieve wide range operation, fast lock and process…
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2004
2004
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs
Y. Jeon
,
J. Lee
,
+4 authors
Hong-June Park
IEEE Journal of Solid-State Circuits
2004
Corpus ID: 45190075
The conventional register-controlled delay locked loop (RCDLL) with a single delay line requires a complex logic circuit…
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2001
2001
An 8-Bit, 100-MHz low glitch interpolation DAC
Yijun Zhou
,
Jiren Yuan
ISCAS . The IEEE International Symposium on…
2001
Corpus ID: 12923139
This paper describes an 8-Bit, 100-MHz current steering CMOS low glitch interpolation digital to analog converter (DAC). It…
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1996
1996
Blind multichannel adaptive MMSE equalization with controlled delay
David Gesbert
,
Pierre Duhamel
,
Sylvie Mayrargue
Proceedings of 8th Workshop on Statistical Signal…
1996
Corpus ID: 62551039
The article addresses the problem of optimal blind linear symbol recovery, using the channel diversity induced by a sensor array…
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Highly Cited
1994
Highly Cited
1994
An integrated 16-channel CMOS time to digital converter
C. Ljuslin
,
J. Christiansen
,
A. Marchioro
,
O. Klingsheim
1994
Corpus ID: 61921441
An integrated 16-channel Time to Digital Converter (TDC) for use in the NA48 experiment at CERN has been developed in a 1 /spl mu…
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1993
1993
Irreducible Error Performance of a Digital Portable Communication System in a Controlled Time-Dispersion Indoor Channel
I. Crohn
,
G. Schultes
,
R. Gahleitner
,
E. Bonek
IEEE J. Sel. Areas Commun.
1993
Corpus ID: 12187123
The authors investigated experimentally, analytically, and by simulation the irreducible errors such as error floor for high…
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Highly Cited
1983
Highly Cited
1983
Calculating te maximum mean data rate in local area networks
B. Stuck
Computer
1983
Corpus ID: 21016336
In February 1980 a group of people met in San Francisco, CA, USA, to form Project 802: Local Area Network Standards, sponsored by…
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