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Clock network

Known as: Clock strata, Clock stratum, Clock system 
A clock network or clock system is a set of synchronized clocks designed to always show exactly the same time by communicating with each other. Clock… 
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Related topics

Related topics

10 relations

Broader (1)

Broadcast engineering
Master controlMaster/slave (technology)ModemRS-232

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Review
2012
Review
2012
Novel Approaches and Developments in Colon Specific Drug Delivery Systems- A Review
Colon specific drug delivery has gained increased importance not for the treatment of local diseases associated with the colon… 
2010
2010
Two-Phase sinusoidal Power-Clocked Quasi-Adiabatic Logic Circuits
This paper presents the design and performance analysis of the dual-rail encoded and sense-amplifier structured 2N–2P, 2N–2N2P… 
2009
2009
Dynamic frequency-switching clock system on a quad-core Itanium® processor
The 700mm2 65nm Itanium® processor codenamed Tukwila [1] integrates four cores and a system interface with six QuickPath… 
2005
2005
A 90nm variable-frequency clock system for a power-managed Itanium/sup /spl reg//-family processor
A clock-generation system delivers fixed- and variable-frequency clocks for adaptive power control on a 1.7 B-transistor dual… 
2005
2005
Diurnal Variation of Plasma Arginine-vasopressin in Pregnant and Non-pregnant Goats ( Capra hircus )
Skotnicka E.: Diurnal Variation of Plasma Arginine-vasopressin in Pregnant and Non-pregnant Goats (Capra hircus).Acta Vet. Brno… 
2005
2005
Initialization of a wireless clock distribution system using an external antenna
A compact wireless clock distribution system with an external planar array antenna which can provide phase uniformity suitable… 
2002
2002
Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips
To debug a digital chip with a scan-based debug methodology, the chip is stopped at a certain point in time in the application… 
1999
1999
A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive
A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power… 
1997
1997
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations
This paper addresses the problem of clocking large high-speed digital systems, as well as deterministic skew modeling, a related… 
1997
1997
A narrow-band delta-sigma frequency-to-digital converter
This paper describes a novel frequency-to-digital conversion technique based on the D flip-flop frequency delta-sigma concept. It… 
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