Clock network

Known as: Clock strata, Clock stratum, Clock system 
A clock network or clock system is a set of synchronized clocks designed to always show exactly the same time by communicating with each other. Clock… (More)
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Topic mentions per year

Topic mentions per year

1956-2017
0204019562016

Papers overview

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2011
2011
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by… (More)
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2009
2009
Clock network synthesis (CNS) is one of the most important design challenges in high performance synchronized VLSI designs… (More)
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Highly Cited
2009
Highly Cited
2009
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power… (More)
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Highly Cited
2004
Highly Cited
2004
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock… (More)
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Highly Cited
2004
Highly Cited
2004
A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a… (More)
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2001
2001
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes… (More)
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Highly Cited
2001
Highly Cited
2001
In this paper, a global clock network that incorporates standing waves and coupled oscillators to distribute a high-frequency… (More)
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Highly Cited
2000
Highly Cited
2000
A global clock distribution strategy implemented on several microprocessor chips is described. The clock network consists of… (More)
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Highly Cited
2000
Highly Cited
2000
A novel clock network composed of multiple synchronized phase-locked loops is analyzed, implemented, and tested. Undesirable… (More)
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Highly Cited
1998
Highly Cited
1998
A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop… (More)
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